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dffwewe
- 自己刚编写的vhdl语言来实现的D触发器，自我感觉还可以，也通过了编译，如果有需要就下载去看看吧-just prepared their own language to achieve vhdl D flip-flop, but also a sense of self, but also through a compiler, If there is a need to look at the downloaded Look here
beipin_4
- 自己编写的vhdl语言来实现的四倍频电路，自我感觉还可以，也通过了编译，如果有需要就下载去看看吧-prepared vhdl own language to achieve the four frequency circuit, a sense of self, can also, through a compiler, If there is a need to look at the downloaded Look here
lpm_inv0
- 自己编写的vhdl语言来实现的lpm_inv0电路，自我感觉还可以，也通过了编译，如果有需要就下载去看看吧-prepared vhdl own language to achieve the lpm_inv0 circuit, but also a sense of self, also passed the compiler, if there is a need to look at the downloaded Look here
VHDLcontrolCurentmotor
- VHDL设计直流电机的典型例子，适合教学或自学案例-VHDL design Motor typical example, for teaching or self-Case
VHDLdesignGame
- 用VHDl设计一个小游戏的例子，适合教学或自学使用-VHDl design with a small example of the game, suitable for use or self-teaching
VHDLdesignURA
- 用VHDL编写的URAT程序，适合教学或自学使用-VHDL URAT prepared by the procedures for the use of teaching or self -
auto.self.machine.VHDL
- 货物信息存储，进程控制，硬币处理，余额计算，显示等功能。
数据结构c描述习题集答案
- 减1计数器 一、设计要求 用Verilog HDL语言设计一个计数器。 要求计数器具有异步置位/复位功能，可以进行自增和自减计数，其计数周期为2^N（N为二进制位数）。 二、设计原理 输入/输出说明： d：异步置数数据输入； q：当前计数器数据输出； clock：时钟脉冲； count_en：计数器计数使能控制（1：计数/0：停止计数）； updown：计数器进行自加/自减运算控制（1：自加/0：自减）； load_d-a counter a reduction, design requirem
Sdram_Control_4Port.Verilog写的sdram的控制器
- 已经验证可用。此代码为Verilog写的sdram的控制器，可以由用户的使用而加载到自己的项目中自行开发。,Have verified that is available. This Verilog code written sdram controller, can be loaded into the user' s use of their own self-developed projects.
car1.rar
- 基于FPGA控制的红外循迹小车，八个传感器，利用PWM进行控制转弯和前进后退，可以自启动,FPGA-based infrared tracking control car, eight sensors, using PWM to control turning and forward and back, you can self-starting
VHDL100
- 一套不错的VHDL例子，附带清华大学自主研制的仿真器，仿真结果都有的，希望给您提供很方便-VHDL a good example of self-developed with Tsinghua University, simulator, simulation results are, I hope to provide you with easy
Verilog_SOM
- Verilog编写的SOM(自适应神经网络算法)-Verilog written SOM (self-adaptive neural network algorithm)
899207KEYBOARD_DEC-vhdl
- 数字平律己的设计非常实用 黄永显示早设计大方ijasd-The design of digital self-Ping Wong Wing-show as early as practical design Dafang ijasd
digi_clock2.7z
- 數位電子時鐘 用自製圖檔製成 不是用quartusII 內建的圖檔製成 -Digital electronic clock with self-image made of instead of the built-in image quartusII made
Quartus2_VerilogRoutine
- 该文档是基于QUARTUS2_6.0的Verilog试验例程，其中附有工程源码，对于初学者是最好的例程！它是本人花费一年多自学后写的例程，以便初学者入门，里面附有很多图解，很详细！-The document is based on the Verilog test QUARTUS2_6.0 routines, including an engineering source code, for beginners is the best routine! It is, I spent more
VHDL2
- 成本低廉易于实现非常适合自学自制的出租车计价器VHDL程序-Low-cost and easy to implement very suitable for self-made Taximeter VHDL procedures
03.EDK8.2
- 使用xilinx virtex4芯片，设计环境为EDK，其中包含uart,片外sram操作，flash操作，DDR SDRAM操作，MAC自发自收，audio，video等试验-Xilinx virtex4 use chip design environment for the EDK, which contains the uart, chip sram operation, flash operation, DDR SDRAM operation, MAC spontaneous self-
FPGA-Built-In-Self-Test-and-FPGABIST
- FPGA Built-In Self-Test and FPGABIST
self-drink-seller-verilog-code
- 饮料自动售卖机的verilog代码，实现各种情况下饮料的购买-self-drink seller verilog code
A-novel-approach-to-realize-Built-in-self-test(BI
- A novel approach to realize Built-in-self-test(BIST)