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calculation2
- 用VHDL语言实现0--100范围内简单计算器功能的源代码，包括加减乘除四种运算功能-VHDL 0 -- 100 within a simple calculator function in the source code. including the four arithmetic operations function
calc
- 用FPGA设计的简易计算器,包括按键模块,数码管模块-Use the FPGA design simple calculator, including key module, digital tube module
calculator
- 用VHDL在quartus2下实现的计算器。输入为4*4矩阵键盘，输出为共用数据线的数码管。可以实现简单数学运算、逻辑运算、进制转换、连续运算等功能。-Using VHDL in quartus2 achieve calculator. Input 4* 4 matrix keyboard, the output data lines for sharing of digital control. Can achieve a simple mathematical operations, log
VHDL语言写的简易计算器
- 用VHDL写的简易计算器，包括加减乘除，除法器用加法器和乘法器组成-Write simple calculator with VHDL, division, including add, subtract, multiply and divide adder on time-multiplier and used
calculator
- VHDL编写计算器，功能包括：加，减，乘，除。通过keypad输入及输出-Calculator written with VHDL
61EDA_D1051
- 用VHDL编写的计算器：能实现简单的加减乘除四则运算-Prepared using VHDL calculator: to achieve simple addition and subtraction, multiplication and division four computing
erwertwerwe
- 用VHDL编写的计算器：能实现简单的加减乘除四则运算-Prepared using VHDL calculator: to achieve simple addition and subtraction, multiplication and division four computing
calc_v2_s3eboard
- Simple calculator EDK design implemented on Digilent S3EBOARD using Microblaze soft-core CPU. Input: PS/2 keyboard, output: VGA monitor.
key_led
- 简易计算器的键盘和LED显示，很简单，但也可以说很复杂-Simple calculator keyboard and LED display, very simple, but can also be said very complicated
verilog_calculator
- 用verilog编写的简易计算器代码。通过一位全加器组成电路，可以实现加法、减法和乘法，并在七段数码管上显示出十进制的结果。-Simple calculator with code written in verilog. Composed by a full adder circuit, can add, subtract and multiply, and in the seven-segment LED display on the decimal result.
verilog_calculator
- 一个Verilog写的简易计算器。能进行二进制加减乘除运算，操作数通过按键输入并用数码管显示。当按下运算符号键后，计算器进行两个数的运算，数码管将结果显示出来。-A simple calculator written in Verilog. Binary addition and subtraction to multiplication and division, operating a few keystrokes and use digital display. When the pres
calculator--EDA
- EDA可编程逻辑设计 设计一个简易十进制以内的计算器 可以利用按键和数码管作为计算器的输入和输出，能完成十以内的整数的加、减、乘、除（商和余数）运算，预算结果可以是正/负数，结果的绝对值可以超过十，且能够正确显示。-EDA design of programmable logic to design a simple decimal calculator can be used within the tube as the calculator keys and digital inputs a
VHDL
- It s a simple calculator of addition and multiplication using a simple stack, with multiple test benches. The files test-button and debounce are for the use on a board for the correct functionality of the input buttons.
Simple-calculator
- Simple calculator using VHDL coding
counter
- 一个基于赛林思FPGA板子的简单的计算器的例子，适合初学者学习！-A LinSi based on the FPGA board simple calculator example, is suitable for beginners to learn!
verilogcalculator
- 简易的计算器，可实现加减乘除运算，采用verilog编写-Simple calculator, addition, subtraction operation can be realized using verilog prepared
calculator
- 简易的计算器，可实现加减乘除运算，采用verilog编写-Simple calculator realized by verilog,which could operate addition and subtraction process
123
- 基于FPGA的简单计算器系统的设计，使用了vhdl与verilog语言，附有文档介绍-Simple calculator system based on FPGA design using vhdl verilog language, with document describes
Calculator.v
- Verilog实现简易计算器，用数码管显示结果-Verilog achieve simple calculator, with digital display results
calculator
- 7位十进制计算器设计，可实现简单计算式的计算，内附testbench文件-Seven decimal calculator designed to achieve a simple calculation formula, enclosing testbench file