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H16550_2[1].0V
- 专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550 ，包含完整的使用说明手册、testbench、可综合，如果被网站认可，将继续上传其余的几个更好的core。-specialized processor and peripheral interfaces famous ipcore CAST product manufacturers UART H16 550, including full use manual testbench can be integrate
LED七段译码
- 初次上传文件，采用文本格式编辑内容，不知道是否妥当，如有不便之处，敬清各位原谅。-initial upload documents using text format editorial content, I do not know whether they are appropriate, if any inconvenience, King - forgive me.
CPLD_CODE12
- 最后一个了，其他的未经验证，以后验证成功后再上传-final one, the other is untested and proved to be successful, then later upload
PUKverilogPPT1-9PAGE
- 我收藏的北京大学的verilog的PPT,希望对大家有用,这是1-9章,随后上传剩下的-collection of the Beijing University verilog the PPT, a member of the useful, which is 1-9 chapter Subsequently the remaining Upload
FPGA-CPLD_DesignTool(example3-4)
- FPGA-CPLD_DesignTool,事例程序3-4陆续上传请需要的朋友下载-FPGA-CPLD_DesignTool. 3 -4 examples procedures have requested upload download a friend in need
PS2keyboard_verilog
- 本实验利用PS2接口实现了与键盘通信，并将键盘的按键编码通过UART接口上传给PC的超级终端，通过超级终端来观察按键编码是否正确。 -experimental use of the PS2 interface with the keyboard communications, and keyboard buttons coding through UART interface to the PC upload the Super Terminal, Super Terminal throug
the-design-of-16-bit-cpu
- 用vhdl硬件语言设计的16位cpu，上传的压缩包既包含源代码又包含详细的文档说明。-with vhdl hardware design language of the 16 cpu, Upload compressed contains both the source code also contains a detailed document shows.
CPU_16.rar
- vhdl语言的16b cpu代码 全部的代码我会依次上传 另有说明txt文本,VHDL language 16b cpu code all the code I will upload the text otherwise stated txt
KCPSM3.rar
- 这个是在网上下载的picoblaze的资料，里面有些我自己写的使用方法，现在把它上传给大家。如果有需要的可以下载。个人感觉这个8位的软核开发起来有点麻烦，但是使用起来还是很好用的。对于其中的代码，归原作者所有。,This is the picoblaze downloading information, which some use to write my own methods, now upload it to you. If there is a need can be downloade
VHDL_clock
- 关于电子数字钟得FPGA实现，上传来分享一下-Electronic digital clock was on the FPGA, upload to share with you
DDC_DUC
- 数字上下变频FPGA设计的详细介绍资料，还是中文的。很舍不得上传的哦。-FPGA digital down conversion design detailed information, or Chinese. Oh, very reluctant to upload.
all_test_2c5
- 买的开发板上自带的例程，上传与电子爱好的共享-To buy the development of on-board built-in routines, upload and e-loving sharing
VHDL_src_files
- 这些是我在学习VHDL语言的过程中，自己试验过的以及自己编的一些程序，希望上传和大家分享一下，共同进步！谢谢！-These are my VHDL language in the learning process, and tested their own some of the procedures, I hope to upload and share with you, and common progress! Thanks!
DM12
- vhdl实现的一个十字路口交通灯。上传和大家一起分享。-VHDL realization of traffic lights at a crossroads. Upload and share.
watchver
- 一个VHDL编写的时钟的程序，全部源代码打包上传-The clock to prepare a VHDL process, all source code packaged Upload
connect20090223
- fpga从FIFO读数据并上传到双口ram中。-FPGA read data from the FIFO and upload it to dual-port ram Medium.
DP8051_FREE
- Free 8051 core upload
Upload
- Hello Everyone, this site provides useful document to students like me those who are starts doing project in Programming field.
Common_multiplier_verilog_design
- 上传文件为：常用乘法器verilog设计.rar-Upload files as follows: common multiplier verilog design. Rar
Common_adder_verilog_design
- 上传文件为：常用加法器verilog设计.rar-Upload files as follows: common adder verilog design. Rar