搜索资源列表
Arbiter
- Arbiter.v verilog实现 三路请求，使用循环策略的仲裁器 含有看门狗电路-Arbiter.v Verilog achieve three road request, the use of recycled strategy for containing the arbitration watchdog circuit
vga.niosII.compent.v
- 在cyloneIIFPGA平台下设计完成测试通过的VGA控制器代码。显存留在系统的SDRAM中，用FIFO作为缓冲。-in cyloneIIFPGA platform design is completed tests through the VGA controller code. RAM in the system SDRAM, and use as a FIFO buffer.
magnitude
- Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algori
wb_rtc
- // -*- Mode: Verilog -*- // Filename : wb_master.v // Descr iption : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : U
Verilog_VGA.rar
- 程序实现的功能是在VGA显示器上显示彩色条纹，共8种颜色，可以使用嵌入式逻辑分析仪观测信号。,Procedures for the realization of the function is displayed on the monitor in the VGA color stripes, a total of eight kinds of colors, you can use the embedded logic analyzer signal observation.
fifo
- 异步fifo，用Verilog编写，包含testbench，已经通过modelsim调试，内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave
TestLED2C5
- 文件中有CPU8051V1.vqm具体使用的例子和CPU8051V1.vqm文件，适用于quartusii软件中对单片机的嵌入练习和使用-CPU8051V1.vqm document specific examples of the use of CPU8051V1.vqm documents, quartusii software for single-chip embedded in the exercises and the use of
LCD12864
- 利用FPGA在12864液晶屏上显示汉字。配置IO后可直接使用-Use of FPGA in the 12864 character LCD display. IO configuration can be used directly after
EX
- Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge.
1_LAB
- Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge.
DE2_LCM_CCD
- DE2 CCD数码相机源代码，下载即可使用。方便学习。-DE2 CCD digital camera source code, you can use to download. Facilitate learning.
dac
- 0～5伏可调数字电压源，以5伏为基准电压，数码管显示当前电压值，使用VHDL语言实现，程序都加了注释，方便阅读。 -0 ~ 5 V digital voltage source adjustable to 5 V for the voltage reference, digital tube displays the current voltage value, the use of VHDL language, the program notes are added to facilita
vga_module
- This source use to display a 256x256 RGB image from SRAM on a CRT monitor.You can use this to filter colors of the image.Image is loaded into SRAM by using DE2_control_panel
hdb3
- hdb3编码源程序完整版，内含插B，插V程序，功能完整，欢迎下载-library ieee use ieee.std_logic_1164.all entity hdb3 is port(codein: in std_logic clk : in std_logic clr : in std_logic --复位信号 codeout: out std_logic_vector
Circuit-Design-with-VHDL
- VHDL数字电路设计教程 作者：（巴西）佩德罗尼（Pedroni,V.A.） 著，乔庐峰 等译 本书采用将数字电路系统设计实例与可编程逻辑相结合的方法，通过大量实例，对如何采用VHDL进行电路设计进行了全面阐述。 本书分为三大部分：首先详细介绍VHDL语言的背景知识、基本语法结构和VHDL代码的编写方法；然后介绍VHDL电路单元库的结构和使用方法，以及如何将新的设计加入到现有的或自己新建立的单元库中，以便于进行代码的分割、共享和重用；最后介绍PLD和FPGA的发展历史、主流厂
robust_fir_latest.tar
- RobustVerilog generic FIR filter In order to create the Verilog design use the run.sh scr ipt in the run directory (notice that the run scr ipts calls the robust binary (RobustVerilog parser)). The filter can be built according to 3 differe
DAC-use-verilog
- 用verilog写的TLV5620芯片的DAC转换代码，核心文件dac.v，能进行实现，不仅仅是行为级描述-Written with verilog conversion code TLV5620 DAC chip, the core file dac.v, can be achieved, not just behavioral descr iption
DI-S-AND-V
- 这个程序是为了区分SIGNAL和VARIABLE在不同情况下要怎样使用的例程，程序中使用了三种情况来说明问题-This program is designed to differentiate between routine SIGNAL VARIABLE in different situations and how you want to use, the program uses the three cases to illustrate the problem
float_2_int.v
- 最全的，最简单，32位浮点数转整数，32位整数转浮点数，直接可以移植，已经测试过好用。(The most complete, the simplest, 32 bit floating-point integer, 32 integer floating point number, can be directly transplanted, has been tested, easy to use.)
total
- 综合应用程序，包括VGA显示，温度测量等，便于初学者掌握使用verilog HDL语言的进行综合设计和使用(Comprehensive application program, including VGA display, temperature measurement and so on, is easy for beginners to master and use Verilog HDL language for comprehensive design and use.)