文件名称:wb_rtc
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// -*- Mode: Verilog -*-
// Filename : wb_master.v
// Descr iption : Wishbone Master Behavorial
// Author : Winefred Washington
// Created On : 2002 12 24
// Last Modified By: .
// Last Modified On: .
// Update Count : 0
// Status : Unknown, Use with caution!
// Descr iption Specification
// General Descr iption: 8, 16, 32-bit WISHBONE Master
// Supported cycles: MASTER, READ/WRITE
// MASTER, BLOCK READ/WRITE
// MASTER, RMW
// Data port, size: 8, 16, 32-bit
// Data port, granularity 8-bit
// Data port, Max. operand size 32-bit
// Data transfer ordering: little endian
// Data transfer sequencing: undefined
// Filename : wb_master.v
// Descr iption : Wishbone Master Behavorial
// Author : Winefred Washington
// Created On : 2002 12 24
// Last Modified By: .
// Last Modified On: .
// Update Count : 0
// Status : Unknown, Use with caution!
// Descr iption Specification
// General Descr iption: 8, 16, 32-bit WISHBONE Master
// Supported cycles: MASTER, READ/WRITE
// MASTER, BLOCK READ/WRITE
// MASTER, RMW
// Data port, size: 8, 16, 32-bit
// Data port, granularity 8-bit
// Data port, Max. operand size 32-bit
// Data transfer ordering: little endian
// Data transfer sequencing: undefined
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下载文件列表
wb_rtc/
wb_rtc/bench/
wb_rtc/bench/Verilog/
wb_rtc/bench/Verilog/clkrst.v
wb_rtc/bench/Verilog/tb_top.v
wb_rtc/bench/Verilog/timescale.v
wb_rtc/bench/Verilog/wb_master.v
wb_rtc/rtl/
wb_rtc/rtl/Verilog/
wb_rtc/rtl/Verilog/wb_rtc.v
wb_rtc/bench/
wb_rtc/bench/Verilog/
wb_rtc/bench/Verilog/clkrst.v
wb_rtc/bench/Verilog/tb_top.v
wb_rtc/bench/Verilog/timescale.v
wb_rtc/bench/Verilog/wb_master.v
wb_rtc/rtl/
wb_rtc/rtl/Verilog/
wb_rtc/rtl/Verilog/wb_rtc.v
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