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people4
- 这是我自己写的4人表决器源码，在xilinx Spartan3E 上已经调试成功，拿出来与大家分享！-that I wrote four voting machine source code, In xilinx Spartan3E debugging has been successful, with the show to share with you!
biaojueqi
- 这是一个用VHDL语言实现的非常实用的表决器-This is a VHDL language with the very practical voting machine
seven
- 这是我在ISP编程实验中独立编写的采用结构化描述的一个七人表决器，通过独特的3次映射一位全加器的方法从而实现七人表决器的功能，与网络上任何其他的七人表决器源码决无雷同。-This is my ISP programming in an independent experiment using a structured, prepared as described in a seven-member voting machine, through a unique 3 times a full a
22
- VHDL语言实现三人表决器控制电路，有优先级自主设定等功能-VHDL language to achieve three of the voting machine control circuit, a priority setting features such as autonomous
sevenvote
- 本设计师一个7人表决器，用7个开关作为7个输入变量，输入变量是 1 时表示赞同，输入变量为 0 时表示不赞同。-The designer of a voting machine 7 with 7 switch 7 as input variables, input variables is a' 1 ' when agreed input variables for the' 0' that do not agree with.
Quartus
- 1.七段数码管译码器 2.4人表决器 3.4进制加减法计数器~具有进位和借位功能-1. Seven-Segment LED Decoder 2.4 M 3.4 people voting machine counters ~ with addition and subtraction and by-bit binary function
VHDL
- 这是关于VHDL的五个简单程序，跑马灯、简单时钟、4*4键盘、计价器、7人表决器。-This is about the five simple VHDL program, marquees, a simple clock, 4* 4 keyboard, the meter, 7 voting machine.
5renduoshuVHDL
- 5人多数表决VHDL源代码，数码管可以显示倒计时时间和通过的人数-5 Most of the voting machine
biaojue
- VHDL编写的七人表决器，有做课程设计的有福了-Written in VHDL seven voting machine, there are so blessed Oh curriculum design
chap5_voter5
- FPGA学习资料-VHDL语言实现的表决器-FPGA-VHDL language learning materials in the voting machine
bjq3
- 表决器 三人表决 2个人以上通过就亮灯，不然不亮-Voting machine
The.design.of.the.voting.machine
- 表决器的设计 设计一个三人的表决器，其中有二人以上同意则投票通过。演示结合实验箱上A区、J区的LED及按键。工作过程如下：带锁的按键按下时，按键上的灯亮表示投票同意；按键松开时，灯熄灭表示投票反对；SW1-SW3这三个按键是3人的投票键，L1灯亮表示投票通过，且蜂鸣器响；L1灯熄灭表示投票未通过，且蜂鸣器不响。利用原理图和VHDL编程相结合的方法来实现-The design of the voting machine
fourone
- 四选一数据表决器，ABCD四选一，选择一个输出端口输出所要的电平。实现数据表决-Four data select a voting machine, ABCD four-pick one, choose an output port to the output level. Data division
biaojueqi
- 四路表决器。原理图设计。经过时序仿真验证。-Four voting machine. Schematic design. After a timing simulation.
vhdl
- 三人表决器（三种不同的描述方式）以及通用寄存器-Three voting machine (a descr iption of three different ways), and general-purpose registers
CPLD-Three-voting
- CPLD/FPGA 设计实例手册 用VHDL语言设计三人表决器 用原理图输入的方式设计三人表决器 用verilog-HDL语言设计三人表决器-CPLD/FPGA design example manual Three of the voting machine VHDL language Schematic design of a three-member voting Verilog-HDL language design three-member voti
Three-of-the-voting-machine.doc
- 三人表决器，是三个人进行投票表决。投票结果是为三人投的多数-Three of the voting machine
Three-voting-machine
- 三位表决器，源代码-Three voting machine
VHDL-design-seven-people-voting
- 1、 熟悉VHDL的编程。 2、 熟悉七人表决器的工作原理。 3、 进一步了解实验系统的硬件结构。 -1, familiar with VHDL programming. 2, familiar with the seven voting machine works. 3, to further understand the experimental system hardware architecture.
Seven-voting-machines
- 用verilog编写的七人表决器代码·可以实现七人表决超过四人就通过的功能-Written in verilog seven voting machine code can be achieved seven people to vote on the adoption of more than four functions