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cpld
- 西安工业大学电信学院信息与通信系综合设计报告 -Xi an University of Technology Institute of Information and Communications Department of Telecommunications comprehensive design report
1
- fpga经验谈(西安大唐电信)，好不容易搜集过来的。-fpga experience (Xi' an Datang Telecom)
main
- 交通信号灯 原代码 西安交通大学 电信学院 FPGA设计课下作业-Traffic lights of the original source, Xi' an Jiaotong University School of FPGA design course telecommunication operating under the
Chapter11-13
- 第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个
first-follow
- first follow集合生成器 我晕。还嫌我说的少-first bu jiushi shang chuan dong xi ma
xlinx
- xilinx在天津的培训 是其大学培训计划的成功结果-xilinx training in Tianjin is the successful outcome of university training programs
FPGAshiyan(11)
- FPGA入门系列实验教程——实验十一数码管动态显示-Getting Started with FPGA tutorial series of experiments- Experiment XI LED dynamic display
singlecircle_cpu
- 实现十一条指令的单周期处理器，运用Verilog语言，顺利执行，仿真正确。-To achieve single-cycle instruction processor XI, the use of Verilog language, the successful implementation of the simulation is correct.
bahe
- 拔河游戏机 的VHDL语言，内部分为6个模块。-bahe you xi ji
VHDL-and-DLC-design
- VHDL硬件描述语言与数字逻辑电路设计 西安电子科大出版-VHDL hardware descr iption language and digital logic circuit design Xi' an Electronic Science and Technology Publishing
chap11
- 这是关于ＦＰＧＡ第十一节的实验代码可以参考 特权同学的深入玩转ＦＰＧＡ一书进行学习-This is the book depth Fun FPGA FPGA section XI of experimental code can refer to the privileged students learning
ASIC
- 西安交大asic课件，对于数字集成电路的学习有帮助，经典-Xi' an Jiaotong University asic courseware for learning to help digital integrated circuits, classic
dianziqin2--lcd
- 基于Altera公司的开发板DE2--EP2C35F672C6，制作的电子琴，实现do、re、mi、fa、sol、la、xi、do八个音调，并可选择手动或自动播放，其中手动播放可实现存储与回放。并可实现液晶屏对音符的显示。-Development board based on Altera' s DE2- EP2C35F672C6, making organ, realize do, re, mi, fa, sol, la, xi, do eight tones, and can choo
LCD
- LCD的循环输出，在Quartus二的环境下进行开发，DE2-70的开发板，用VHDL语言编写-LCD de xúnhuán shūchū, zài Quartus èr de huánjìng xià jìnxíng kāifā,DE2-70 de kāifā bǎn, yòng VHDL yǔyán biānxiě
Soc_Audio_v5
- DE1 audio soc,xue xi audio process by Altera soc FPGA-DE1 audio soc
xi
- xilinx screenshot vhdl verilog