搜索资源列表
s_filter
- fpga实现图象滤波,实时的实现对输入图象的形态学滤波-FPGA realization of image filtering, real-time realization of the input images of morphological filtering
VGA
- 用VERILOG写的VGA显示代码,经本人调试确定可以正常运行-VERILOG written with VGA display code, as I confirmed to be the normal operation of debugging
fpga-jpeg
- fpga based jpge 压缩算法, 性能不错,-fpga based jpge compression algorithm, performance good,
ddachabu
- 数控里的数字积分,微分插补。 DDA插补-NC integral to the figures, differential interpolation. DDA interpolation
VGA_change
- 程序可以在VGA显示器上以800x600分辨率显示方波示例和字母示例,源文件保存在src目录,QII的工程文件保存在Proj目录。-Program can display in VGA resolution display to 800x600 square sample and letters examples, source files stored in the src directory, QII the project file stored in the directory Proj
IMDCT
- 主要是进行IMDCT变换的源码,供大家参考使用,希望能得到大家的认可。-Mainly IMDCT transform source for your use, we hope to be recognized.
dct
- 主要是进行DCT变换的源码,供大家参考希望能得到大家的认可。-Mainly DCT transform source for your information we hope to be recognized.
jpeg_rgb
- 这是JPEG图像压缩的RGB转换的源代码,其中还包括了它的仿真测试代码,希望能帮助到大家。-This is the JPEG image compression of RGB conversion source code, including its simulation test code, hoping to help you.
video_process_base_on_DSPandFPGA
- 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型 化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间 利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管
vga_line
- 该项目在VGA显示器上显示一条从屏幕左上角开始,呈135度角的水平线。使用VerilogHDL语言编写,在Altera公司的QuartusII开发环境下验证通过。-The project was displayed on a VGA monitor from the top left corner of the screen to start, showing 135-degree angle of the horizon. VerilogHDL language used in Altera&
dilation1
- 用VHDL語法去表示實現dilation,-VHDL grammar used to express achieve dilation,
window_9
- 利用vhdl內的block組成一次讀取9個像素的模組-The use of VHDL within the block comprising a 9-pixel reading module
VGA_move
- 单色扫频,vga接口程序,实现蓝红绿色的显示和运动-Sweep monochrome, vga interface program, the implementation of green blue red sports display and
smart
- 这个一个好和序,一个美丽学校的虚拟现实,此程序很好!-This a good and order, a Beauty School of virtual reality, this program very good!
fft16ref0
- vhdl语言按fft接口标准把数字图像信号转换成标准VGA格式。适合做学习试验 -implementation_fft
median_filter
- 实现图像中值滤波的VerilogHDL源代码-Median_filter VerilogHDL Code
vga
- display text to vga.
sim_b
- Scheatic of SIM 300E GSM modem
TFT2VGA
- 可以从TFT 转vga-TFT TO vga !!!!!!!!!!!
POCREPORT
- 为充分利用CPU的运行效率,采用中断功能设计并行输入输出接口,以达到缓解CPU高速运行速度与外设低速缓冲间的矛盾。-To take full advantage of the efficiency of CPU operation, interruption of functional design using parallel input-output interface, in order to alleviate the CPU speed and high-speed periphera