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full_add
- 一个用VHDL语言编写的8位全加器，并且扩展了减法功能，带有状态位的判断。-a VHDL prepared by the eight-adder, and extends the subtraction function, with state-of judgment.
0809
- 0809控制器程序 VHDL编写的 仅供参考-0809 controller procedures prepared by the VHDL is for reference only
washing
- 洗衣机控制器 做课程设计的同学可以下了看看 用vhdl语言做的 -washing machine controller design courses so students can see where the use of the VHDL language
VHDL100li
- 100个关于VHDL的例子程序，总有几个会适合你-100 examples of VHDL procedures, and the total number would be suitable for you
VHDL_conduct
- 这是VHDL数字系统设计的试验指导书，里面有许多好的例子。-VHDL digital system design guide the pilot, there are many good examples.
mc8051_core
- 一个用VHDL写的8051的内核,很方便集成到FPGA里.-a written VHDL 8051 kernel, is a convenient integrated into the FPGA Lane.
turbo_VHDL
- Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * M
112312312312312
- 计时器的vhdl码 -timer code in vhdl
clk_div3
- vhdl语言写的基数分频器，多平台，通过MODESIM仿真-vhdl language to write the base dividers, multi-platform, through simulation MODESIM
usb_funct
- USB接口的VHDL源码，支持Verilog HDL程序-USB VHDL source code, supports Verilog HDL procedures
ad_s_machine
- 用ＶＨＤＬ实现Ａ／Ｄ转换的状态机的控制，所用的开发软件是ＱＵＡＴＴＵＳ６.０-using VHDL A / D conversion of the state machine control, used in the development of software is QUATTUS6.0
20060411131929393
- SOURCE INSIGHT的VHDL语法插件，SOURCE INSIGHT支持自动完成等功能，是一个不错的硬件语言编辑分析器-SOURCE INSIGHT VHDL syntax plug-ins, SOURCE INSIGHT done automatically, and other support functions, is a good language editing hardware analyzers
cymometer
- vhdl 实现的频率计，可以到实验箱上实现．-vhdl achieve the frequency, it can be to achieve experimental box.
SPI-PRT
- 昨天在论坛上看到有人帖出了他写的并串转换VHDL代码，但是他自己说有问题，但是不知道怎么改。我大概看了一下，发现思路还是比较乱的。于是就写下了我自己的并串转换代码。-yesterday at the forum see someone points out his writing and string conversion VHDL code, But he said there are problems, but does not know how reform. I probably wat
95108325
- 通过CPLD实现串行通信之VHDL语言，好看易懂-through CPLD serial communications VHDL, pretty easy to understand
jicifenpinqi
- 别人编写的奇次分频器，用VHDL写的，我已经在QUARTUS上验证过了-others prepared by the odd dividers, VHDL write, I have QUARTUS tested the
jhvhjhk
- 乒乓球游戏机实验报告实验人： 大火虎设计课题： 用VHDL设计一个乒乓球游戏机,用开关来摸拟球手及裁判,用LED来模拟乒乓球,采用每局十一球赛制,比分由七段显示器显示. 设计思路： 采用按功能分块,将整个电路分成若干子程序,利用不同的子程序来实现记分，显示，键盘控制。设计过程： 1) 对4MHZ信号进行分频,得到所需的1HZ,及七段显示器所需的频率.存为CLOCKMAKE.VHD(注:仿真时所加的信号频率比这要高。)。 2) 设计一个子程序来描述裁判,左击球手,右击球手的动作对LED显示的影响,
cnt10
- 用VHDL语言编的带有异步清零功能的十进制计数器-using VHDL addendum to the asynchronous reset function with the decimal counter
and1
- 用VHDL语言编写的三位二进制的乘法器，其原理是每位相乘后再错位相加-using VHDL prepared by the three binary multipliers, the principle is that each subsequent dislocation multiplication sum
sub4
- 用VHDL语言编写的两个四位二进制数相减，其结果会出现进位-using VHDL prepared by the two four binary-phase reduction, and the results will be there to rounding