搜索资源列表
turbo_VHDL
- Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * M
usb_funct
- USB接口的VHDL源码，支持Verilog HDL程序-USB VHDL source code, supports Verilog HDL procedures
jicifenpinqi
- 别人编写的奇次分频器，用VHDL写的，我已经在QUARTUS上验证过了-others prepared by the odd dividers, VHDL write, I have QUARTUS tested the
and1
- 用VHDL语言编写的三位二进制的乘法器，其原理是每位相乘后再错位相加-using VHDL prepared by the three binary multipliers, the principle is that each subsequent dislocation multiplication sum
sub4
- 用VHDL语言编写的两个四位二进制数相减，其结果会出现进位-using VHDL prepared by the two four binary-phase reduction, and the results will be there to rounding
1_4
- 一对四分用器的VHDL源码,（输入：D ，输出： Y3 Y2 Y1 Y0，另有两个输入控制端S1与S0控制输出选择）-tended to a quarter of VHDL source code, (Input : D, output : Y3 Y2 Y1 Y0. otherwise control the importation of two-S1 and S0 output control options)
ADDER8B
- 8位加法器VHDL 8位加法器VHDL-eight Adder VHDL e ight Adder VHDL eight Adder VHDL 8 Adder VHDL
xianweiji
- vhdl编写的频率计程序，很好用，误差为0
S6_MUSIC
- 上个用VHDL语言写的音乐程序,希望对大家能够有帮助
S4_FENGPING
- 这是一个用VHDL语言写的分频程序,可用得着
lc2
- this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 mode
QPSKvhdl.rar
- QPSK的VHDL调制解调 FPGA设计思路思想,QPSK modulation and demodulation of the VHDL design thinking FPGA
vhdl
- 出租车计费系统的设计 2.1 出租车计费器工作原理 实际中出租车的计费工作原理一般分成3个阶段： （1）车起步开始计费。首先显示起步价（本次设计起步费为7.00元）,车在行驶3 km以内，只收起步价7.00元。 （2）车行驶超过3 km后,按每公里2.2元计费（在7.00元基础上每行驶1 km车费加2.2元）,车费依次累加。 （3）行驶路程达到或超过9 km后(车费达到20元)
i2c_latest[1].tar
- I2C VHDL source code
i2c_master_slave_core_latest[1].tar
- I2C VHDL source code
16b20b_Decoder
- VHDL实现的16B/20B解码器。包含两个8B/10B解码器。采用级联方式实现-VHDL implementation 16B/20B decoder. Contains two 8B/10B decoder. Be achieved by cascading
20080108103305384
- 本系统是采用EDA技术设计的一个简易的八音符电子琴和音乐发生器，该系统基于计算机中时钟分频器的原理，采用自顶向下的设计方法来实现，它可以通过按键输入来控制音响。系统由乐曲自动演奏模块、乐器演示模块琴/乐功能选择模块、音调发生模块和数控分频模块五个部分组成。系统实现是用硬件描述语言VHDL按模块化方式进行设计，然后进行编程、时序仿真、整合。本系统功能比较齐全，有一定的使用价值.-The system is designed using EDA technology with a simple ei
pcm
- 利用VHDL语言和模块化设计实现PCM编译码的功能，整体工程和代码全有。-PCM encode and decode by VHDL in Quartus2.
yima
- vhdl译码的部分源代码，取自硕士学位论文，希望对大家有用。-vhdl coding parts of the source code, taken from the master' s degree thesis, we hope be useful.
VHDL语言实现74LS138的功能
- VHDL语言实现74LS138的功能，简单易懂，方便好学。给大家以参考-The VHDL language 74LS138 functionality, easy to understand, easy studious. For everyone to reference