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dataexecute_decode_verilog
- It is the code for implementing the project titled "The Reconfigurable Instruction Cell Array(IEEE 2008)".
DataFetch_verilog
- It is the code for implementing the project titled "The Reconfigurable Instruction Cell Array(IEEE 2008)".
Cvolatile
- eee.std_logic_arith.all use ieee.std_logic_1164.all use ieee.std_logic_unsigned.all entity PL_auto1 is port ( clk:in std_logic --系统时钟 set,get,sel,finish: in std_logic --设定、买、选择、完成信号 coin0,coin1: in std_logic --5角硬币、1元硬币 price,quan
amr2
- ieee paper on amr codec
