crc串,并行算法:穿行算法实现循环冗余校验码的编码 并行算法实现循环冗余校验码款速编码.-crc serial, parallel algorithms: walk through algorithm encoding cyclic redundancy check code parallel algorithm for cyclic redundancy check code section rate coding.

FPGA用于实现crc16编码的verlog源程序，用到的请下载。-FPGA is used to achieve the the crc16 the encoding of verlog source code used to download.

包含32为乘法器的设计，用verilog语言实现，包括booth编码的实现，booth乘法器的实现，3_2压缩器的实现，4_2压缩器的实现，华伦斯树的实现，以及两个testbench文件用于测试。-Contains 32 multiplier design, verilog language, including booth encoding implementations, booth multiplier implementations, 3_2 compressor implementat