搜索资源列表
PLL-Hardware-Design
- systemiew的功能示例，主要讲述在32位条件下有systemview进行PLL硬件设计和软件仿真的方法-PLL Hardware Design and Software Simulation Using the 32-bit of SystemView by ELANIX
PLL-Hardware-Design
- systemiew的功能示例，主要讲述在32位条件下有systemview进行PLL硬件设计和软件仿真的方法-PLL Hardware Design and Software Simulation Using the 32-bit of SystemView by ELANIX
pll
- 关于PLL 一些经典的文章，大家可以参考一下！-PLL some classic article, we can refer to it!
PLL-setting
- FPGA中锁相环的具体设置方法，可以使系统时钟稳定-Setting method of fpga pll, it make system clock stable.
pll
- pll锁相环编程程序 可以使用 matlab 编程语言-The program can be used PLL phase locked loopThe MATLAB programming language
PLL
- PLL仿真 设计和仿真一个PLL，分析杂散和相位噪声-PLL simulation
three-phase-phase-locked-loop-(-PLL-)
- three phase pll 5 harmunic
Il-PLL-anello-ad-aggancio-di-fase
- PLL Italiano Aggancio di fase anello
pll-matlab
- 通信系统锁相环pll matlab仿真，基于微分方程的一阶、二阶锁相环-Phase-locked loop pll matlab communication system simulation, based on first-order differential equations, second-order phase-locked loop
phase-detector-PLL-demo
- 要用phase detector，可到现在还不知道PLL是什么东东，不知道phase detector是如何实现的。 可叹自己没有把事物的因果分析清楚，可叹国外的人懂的比自己多。感谢国外作者的分享。-phase detector PLL demo
PLL
- 自己用PSCAD软件搭建的锁相环模型，大家多多交流讨论-PLL MODEL
pll
- 用quartus自带的ip核生成的pll代码-use the ip core from quartus ii to generate the programme of PLL.
Phase-Locked-Loop-PLL-lecturer
- 锁相环实验，PLL参数测试，锁相环PLL原理与应用，环路滤波器 -The experimental phase-locked loop, PLL parameter testing, and application of the principle of the PLL loop filter
Qinghua-University-PLL-Lecture
- PLL的设计与频率相应 清华大学的讲义 基于低通滤波器的设计绘制开环增益波特图-PLL DESIGN AND FREQUENCY GENERATION Draw open-loop gain Bode plot based on LPF design
Taiwan-University-PLL-lecture-
- 台湾大学PLL讲义讲稿 讲稿里包括Phase-Locked Loops的工作方式，简化模型，仿真图及其应用。-National Taiwan University PLL lecture scr ipt to include in Phase-Locked Loops work, the simplified model, the simulation diagram and its application
ModelSim-for-PLL
- 基于Verilog在的PLL的IP核仿真测试，环境为ModelSim-Verilog-based IP cores in the PLL simulation test environment for ModelSim
dds-pll
- 0245、DDS-PLL组合跳频频率合成器.rar-0245, the combination of DDS-PLL frequency hopping frequency synthesizer.Rar
digital-PLL
- 收集的关于数字锁相环的理论模型和分析讨论，适用于FPGA的数字电路设计。-Theoretical models and analysis and discussion about digital PLL collected for FPGA-based digital circuit design.
pll
- introduce simulink pll matlab
pll
- A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. While there are several differing types, it is easy to initially visualize as an electronic circu