搜索资源列表
A.spur-free.fractional-N.pll
- A new PLL topology and a new simplified linear model are presented. The new fractional-N synthesizer presents no reference spurs and lowers the overall phase noise, thanks to the presence of a SampleJHold block. With a new simulation methodology it i
PLL
- 国外一篇很好的数字锁相环（PLL）设计文档（解压后PLL.pdf），不可不看呦！
pllverilog 完成pll锁相环的设计
- 基于FPGA的程序编写，完成pll锁相环的设计，实验证明次程序是完整的-FPGA-based programming, complete pll PLL design, experiments show that second program is complete
111
- 数字鉴相器,数字锁相环频率合成系统FPGA的实现,很有借鉴价值-Digital phase detector, digital PLL frequency synthesizer system FPGA realization of referential value
ppl
- 锁相电路是相位锁定环(Phase Locked Loop)的简称，主要由鉴相器、环路滤波、压控振荡器成 。主要是要掌握LabVIEW图形化编程特点，-PLL circuit is phase-locked loop (Phase Locked Loop) for short, mainly by the phase detector, loop filter, VCO into. Mainly to grasp the features of LabVIEW graphical programm
PLL(pdf)
- 锁相环的设计方法介绍（PLL），可作为设计的参考。-Design method for PLL (PLL), can be used as a reference design.
PSIMbasedsimulationmodelofthedesignofPLLPLL
- 基于PSIM的锁相环_PLL_仿真模型设计PSIM-based simulation model of the design of PLL _PLL_-PSIM-based simulation model of the design of PLL _PLL_
pll
- The ltering operation of the error voltage (coming out from the Phase Detec- tor) is performed by the loop lter. The output of PD consists of a dc component superimposed with an ac component. The ac part is undesired as an input to the VCO, h
softwarephaselockedloop
- 在电网电压频率波动或者三相不平衡的情况下,硬件锁相很难准确检测到基波正序的相位。在结合PWM整流器空间矢量解耦控制算法的基础上,将软件锁相环技术应用在PWM整流器控制系统中,并用仿真和实验验证了该方案的可行性。实验结果表明,该方案解决了电网电压频率波动及三相不平衡时的相位同步等问题,并在工程上具有一定参考价值。-Frequency or voltage fluctuations in three-phase unbalanced case, the hardware lock is diffic
A-fast-lock-PLL-charge-pump-design
- 一种快速锁定电荷泵锁相环的设计，采用ADS进行仿真-A fast lock PLL charge pump design
PLL-Hardware-Design
- systemiew的功能示例，主要讲述在32位条件下有systemview进行PLL硬件设计和软件仿真的方法-PLL Hardware Design and Software Simulation Using the 32-bit of SystemView by ELANIX
PLL-Hardware-Design
- systemiew的功能示例，主要讲述在32位条件下有systemview进行PLL硬件设计和软件仿真的方法-PLL Hardware Design and Software Simulation Using the 32-bit of SystemView by ELANIX
PLL-setting
- FPGA中锁相环的具体设置方法，可以使系统时钟稳定-Setting method of fpga pll, it make system clock stable.
pll
- pll锁相环编程程序 可以使用 matlab 编程语言-The program can be used PLL phase locked loopThe MATLAB programming language
PLL
- PLL仿真 设计和仿真一个PLL，分析杂散和相位噪声-PLL simulation
three-phase-phase-locked-loop-(-PLL-)
- three phase pll 5 harmunic
PLL
- 自己用PSCAD软件搭建的锁相环模型，大家多多交流讨论-PLL MODEL
pll
- 用quartus自带的ip核生成的pll代码-use the ip core from quartus ii to generate the programme of PLL.
ModelSim-for-PLL
- 基于Verilog在的PLL的IP核仿真测试，环境为ModelSim-Verilog-based IP cores in the PLL simulation test environment for ModelSim
dds-pll
- 0245、DDS-PLL组合跳频频率合成器.rar-0245, the combination of DDS-PLL frequency hopping frequency synthesizer.Rar