搜索资源列表
rail20100916
- 中文资料，ad9910 dds芯片中文资料。非常全面的翻译，适合所有做pll朋友参考使用-chinese pdf ad9910 dds chip Chinese data. Very comprehensive translation, for all to do with pll reference to a friend
LC72131
- Datasheet PLL LC72131
Nl-diystem
- 新型全数字锁相环在无功补偿系统中的应用New all-digital PLL in reactive power compensation system-New all-digital PLL in reactive power compensation system
huawei-internal-electronic-Course
- 这是花2000多元在华为培训时拷出的内部培训资料。 其中介绍了模拟电子电路元件在通信设备上的应用。 分晶体管 运算放大电路 振荡电路 锁相环 A/D D/A 滤波器 负反馈电路等-This is training in Huawei spent 2,000 yuan out of the house when the copy training materials. Which describes the analog electronic circuit elements in th
simulink
- simulink的数字调制解调仿真。以simulink为基础平台，对2ASK、2FSK、2PSK信号的仿真-Digital modulation and demodulation simulink simulation. The simulink-based platform, 2ASK, 2FSK, 2PSK Signal Simulation
me-lift-f
- MOTOROLA CPU me-lift-f经济型微机电梯控制系统用户手册主控制器采用性能优良稳定的美国MOTOROLA 公司的CPU，系统更可 靠。 MOTOROLA 的CPU 在工业控制领域占有重要地位，是世界上嵌入式处 理器最大的供货商，广泛应用于工业控制、汽车电子、消费电子的各个领域。 MOTOROLA CPU 内部集成看门狗电路,具有极强的抗干扰性能。 采用锁相环技术，能降低 CPU 外部频率，增强干扰能力。-MOTOROLA CPU me-lift-f che
SYNC
- pll phasenregler The ltering operation of the error voltage (coming out from the Phase Detec- tor) is performed by the loop lter. The output of PD consists of a dc component superimposed with an ac component. The ac part is undesired as an in
am_regler
- The ltering operation of the error voltage (coming out from the Phase Detec- tor) is performed by the loop lter. The output of PD consists of a dc component superimposed with an ac component. The ac part is undesired as an input to the VCO, h
freq_regler
- The ltering operation of the error voltage (coming out from the Phase Detec- tor) is performed by the loop lter. The output of PD consists of a dc component superimposed with an ac component. The ac part is undesired as an input to the VCO, h
ordnung2
- The ltering operation of the error voltage (coming out from the Phase Detec- tor) is performed by the loop lter. The output of PD consists of a dc component superimposed with an ac component. The ac part is undesired as an input to the VCO, h
Hybrid_PLL_Design_Tutorial_Yiar_Linn
- Hybrid PLL design techniques
sy01_simulink
- 这是一个锁相环的simulink仿真实现，蛮有用的-This is a simulink simulation PLL to achieve,and it is very useful
A-novel-algorithm-implementing-PLL
- 设计了一种新颖的三相锁相环的设计算法，可以用于不平衡电压的相位检测和跟踪。-A modified soft phase lock loop algorithm improving the performance inDynamic phase tracking and detection of unbalanced voltage
PLL
- 基于锁相环的数字调制解调的分析与设计-phase modulation and demodulation based on PL.
CPandI
- pll仿真,锁相环的设计与simulink下的仿真图。准确的。-pll simulation, phase-locked loop design with simulink under the simulation diagram. Accurate.
MATLAB-pll
- 风力发电机组噪声测试的MATLAB程序，包换声功率级测试以及声压级测试-MATLAB program, the replacement sound power level testing as well as the sound pressure level testing of wind turbine noise test
third_pll
- 本论文介绍了三阶PLL的滤波器的参数设计，给出了统一的公式-This paper describes the parameters of the third-order PLL filter design, given a uniform formula
LC
- 本系统是以FPGA（EP2C8Q240C8）为控制核心，由压控振荡器、PLL倍频器、高频功率放大器、遥控器及LCD显示模块组成的压控LC振荡器。能实现输出正弦波频率在15MHZ~35MHZ步进可调，其最小步进为5002HZ，频率稳定度为10-5。当输出信号的频率为30MHZ、峰峰值稳定在1V左右时，在+12V单电源工作的情况下，功率放大器能实现在50Ω纯阻性和50Ω+20pf容性负载上输出功率大于20mw。LCD显示模块能实时显示输出信号的峰峰值和频率，精度由于10 。-This system
costas_PLL
- costas载波恢复算法 锁相环路，注释很清楚-costas carrier recovery algorithm PLL
inipll
- 在锁相环时钟频率切换过程中，只有当锁相环稳定后CPU才会切换到新的PLL设置。因此在设置完PLLCR后需要等待PLL稳定。PLL的切换时间大约等于131072个输入时钟周期。 -The PLL clock frequency switching process only when the phase-locked loop stable CPU will switch to the new PLL settings. After setting PLLCR need to wait for t