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Grid_Synchronization_of_Power_Converters
- it contains pll model information -it contains pll model information
LM7001PIC16F628
- lm7001 pll fm for veronica modifications
fm_500
- My design about FM PLL project
Matlab-about-pll
- 。在总结前人提出的一些锁相环仿真模型的基础上,用Matlab 语言构建了一种新的适用于全 数字锁相环的仿真模型 对全数字锁相环版图进行了SPICE 仿真,与该模型的仿真结果相验证。-. Built using Matlab language summary of some of the previously proposed phase-locked loop simulation model based on a simulation model of a new applicable t
HCS12X_PE
- 其实HCS12X的时钟很简单，比起ARM，甚至是HCS08的8位MCU，就是一个PLL和BUS COLOCK之间的换算。 很多不人愿意看DATASHEET，图太多了，寄存器也是样不多一个样子，所以往往导致程序出问题。 但是，时钟，CRG这块很重要，是一切模块的基础。 那么，如果你不愿意write code，那么就generate code吧。 -Fact, HCS12X clock is very simple compared to ARM, even HCS08 8-bit
LPC2292
- LPC2292采用PHILIPS LPC2292微处理器，可实现高达60MHz工作频率,片内晶体振荡器和片内PLL。LPC2292是一款基于16/32位ARM7TDMI-S，并支持实时仿真和跟踪的CPU，并带有256 k字节(kB)嵌入的高速Flash存储器-LPC2292 PHILIPS LPC2292 microprocessor, can achieve up to 60MHz operating frequency, on-chip crystal oscillator
ADLL-verilog-code
- 数字锁相环的设计代码，完整的，希望能帮到大家-PLL phase-locked loop
PLL_performance-_simulation_and_design
- PLL performance,simulation and design
frequency-synthesis
- 常用锁相环芯片参数，功能，使用环境。频率合成发展的历史及前景-Common PLL chip parameters, function, use of the environment. To frequency synthesis history of the development and prospects
PLLs
- PLL: Phase-locked loop
make-PLL-with-matlab
- 用matlab仿真锁相环 来实现载波同步，调频等功能-Use Matlab simulation phase-locked loop to achieve carrier synchronization, FM
NE564D
- 基于NE564D锁相环频率合成器的设计，毕业设计来的-Based NE564D PLL frequency synthesizer design, graduate design come
PLL_100M
- 实现pll分频功能倍频功能可得到fpga说需要的频率实现多的时钟输入-Multiplier pll divide function to achieve functionality available fpga said I need to achieve multi-frequency clock input
FBD
- 为了更好地进行谐波和无功功率的补偿与控制，叶FBD(Fryze一Buchholz一DPenbrock)法的定 义进行了完善，并给出了补偿电流检测的直接法和间接法，在三相电力系统中对FBD间接法进行 了推广研究，利用参考电压进行投影变换，不仅可以检测出功率电流和零功率电流，还可以检测出 基波有功电流、基波无功电流、谐波电流以及任意次谐波电流等，大大拓展了FBD法的应用范围和领域。MATI一AB仿真和实验结果表明了所定义和推广的电流检测方法的正确性和有效性。 -In order to
05537928
- An All-Digital PLL with a First Order N Shaping Time-to-Digital Converter
68693596PLL
- Algorithm PLL for inverter dc-AC
MC33696
- The MC33696 is a highly integrated transceiver designed for low-voltage applications. It includes a programmable PLL for multi-channel applications, an RSSI circuit, a strobe oscillator that periodically wakes up the receiver while a data
05386026
- In a series of papers in recent years new structures for coherent M-PSK (M-ary Phase Shift Keying) receivers were suggested. These include structures for carrier phase detectors for the carrier PLL (Phase Lock Loop), carrier PLL lock dete
Phase-Locked-Loop-FAQ
- 关于锁相环设计经常遇到的一些问题的官方解答.为设计者提供一些参考.-PLL design on some of the problems often encountered in the official answer. Provide some reference for the designer.
PLL_performance-_simulation_and_design
- PLL Algorithm, Perfomance and Design