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setup_pll_design
- PLL设计仿真，验证工具，这是一个很不错的软件-PLL design simulation
VL7013-VLSI
- VL7013 VLSI FOR WIRELESS COMMUNICATION OBJECTIVES: • To study the design concepts of low noise amplifiers. • To study the various types of mixers designed for wireless communication. • To study and design PLL and VCO. •
classic_PLL
- 非常经典的PLL设计讲义，清华大学重点实验室精华总结-PLL design PPT
信号源类题目分析
- 信号源类有实用信号源的设计和制作（第二届，1995年）、波形发生器（第五届，2001年）和电压控制LC振荡器（第六届，2003年）。 实用信号源的设计和制作（第二届，1995年）要求设计制作一个正弦波和脉冲波信号源，频率范围20Hz～20kHz，低频信号源。涉及到的基础知识与制作能力包含：RC振荡器，脉冲振荡器，数字可调电位器，单片机，数字显示与控制等。 波形发生器（第五届，2001年）要求设计制作一个能产生正弦波、方波、三角波和由用户编辑的特定形状波形的波形发生器，频率范围100Hz～20
DSOGI_PLL5
- PLL matlab simulation
The-principle-of-phase-locked-loop
- 主要介绍了锁相环的基本原理，PLL参数测试示例展示，重点分析了CD4046——通用的CMOS锁相环集成电路，MT8870——音调译码器(Tone Decoder)是MITEL 公司所开发生产为一颗常用复频译码IC。-Introduces the basic principles of phase-locked loop, PLL parameter test sample shows, analyzes the CD4046-- generic CMOS PLL IC, MT8870-- ton
PLL_theta
- PLL锁相环的角度生成问题，角度的代入运算前的修正问题，总算是解决了！-PLL PLL angle generation problem, the angle of substitution before the operation to fix the problem, finally solved!
PLL0
- PLL锁相环运用在矢量变换中的matlab的仿真模型，试试看咯！-PLL is used in the vector transformation of matlab simulation model, try slightly!
linearpll
- it is a pll (phase locked loop simulation)
pll_dq
- simulation of pll-dl
suoxianghuan
- 锁相环相关知识，包含二阶 三阶 锁相环的介绍以及编程实例汇总-Phase-locked-related knowledge, presentation and programming examples included 2nd and 3rd order PLL summary
Weard-Saoud
- reseach about PLL design in Arabic
plldemo
- IPLEMENTATION OF PLL IN MATLAB
A-Low-Power-PLL-FM-Transmitter
- for al those who are interested in radio
RDA5807p
- FM单芯片收音IC（RDA5807SP）与 LCD型MCU 相结合，集成度高，外围少，基于DSP数字RF架构，彻底免生产调试。极大地减少了人力，物力，提高生产效率，整体方案比传统PLL方案便宜百分之20以上，性价比高， FM方案成熟，已大批量投产。 本程序RDA5807p驱动程序，是企业级代码，完整规范，可以移植到任何51单片机甚至stm32,毫无压力！ 注意：此方案在iic总线上挂在多个器件，参考价值很高。 -FM radio single chip IC (RDA5807SP)
publ
- PLL and active filter
256-Shunt-Active-Power-Filter-under-unbalanced-ne
- This paper, focus on the study and design of a shunt active power (APF) filter for the compensation of harmonic currents and reactive power in polluted environment and under unbalanced network voltage. In APF design and control, p-q theory was often
fec_code
- The Slow Peripherals Clock Group includes the McBSPs, I2C, and the UART. The input clock to this clock group is taken the output of divider 2 (D2). by default, the divider is set to divide its input clock by four, but the divide value can be chan
MT402_SOP16
- MT402是一种单声道USB麦克风方案，内置sigma-delta ADC、麦克风前置增益放大器、 锁相环、音量增益调节器和USB收发器。它是非常适合USB电脑麦克风录音的应用。即插即用，无需安装驱动程序。-MT402 is a mono USB microphone solutions built sigma-delta ADC, microphone pre-amplifier gain, PLL, volume gain regulator and USB transceiver.
pll
- Phase lock loop presentation