消除组合逻辑产生的毛刺，可以设计一个系统消除在FPGA设计中常见的毛刺现象-To eliminate glitches generated by combinational logic, you can design a system in the FPGA design to eliminate common glitch phenomenon

12-Bit, Ultra-Low Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTER

The errors are caused by labels being used within code blocks. Replace the double colons by REM statements and these samples will all run without a glitch. Better still, don t use comments within code blocks at all, but place them just before the