搜索资源列表
Digital_Logic_Design
- 基于Xilinx ISE入门材料。包含数字电路入门程序。应用于NEXY3开发板。-ISE entry materials based on Xilinx. Contains digital circuit entry procedures. Applied to the NEXY3 development board.
latch
- Abstract—Power is becoming a precious resource in modern VLSI design, even more so than area. This paper proposes a novel architecture for modular, scalable &reusable hybrid constant co-efficient multiplier (KCM) circuit. Comparison is made b
Timing-Analyzer-Guide-3.1i
- Timing analyser for xilinx
piso1
- The following thesis describes the design, the synthesis, and the implementation of pulse width modulation (PWM) in Xilinx Field Programmable Gate Array (FPGA). The contribution of this thesis is the development of PWM in Xilinx
platform_studio_ug
- 找了好久才找到的xilinx platform studio（XPS）的使用文档-Looking for a long time to find xilinx platform studio (XPS) document the use of
improve-k-best
- 研究MIMO系统检测算法理论及其实现方法的基础上，对已证明较优的算法进行结合和改进，提出了一种改进的K—Best检测算法及其实现方案，并通过仿真验证了方案的可行性。该算法采用预测技术和并行排序相结合的方法，降低了计算复杂度；采用并行流水线结构实现，节省了处理时间；并对方案在xilinx公司的Virtex_5系列n)GA中的资源使用情况进行了统计。研究表明，实现方案可以用于MIMO系统检测算法的硬件实现。-Basic research MIMO system detection algorithm
c_pcie_blk_plus_ug341
- XILINX关于PCIE的介绍，有助于XILINX FPGA设计PCIE。-XILINX official documents, PCIE structure in detail, to help carry out PCIE XILINX FPGA design.
lab7_solution
- Lab 7 solution, system generator xilinx
xapp880
- xilinx介绍的高速数据接收方案，介绍了所用芯片和实现框图-High-speed data reception scheme introduced xilinx
Xilinx_PCIe_Core-DMA
- 本文档介绍了一种基于Xilinx Endpoint Block Plus PCIe IP Core，由板卡主动发起的DMA设计。该设计利用通用的LocalLink 接口，所以方便的兼容支持Xilinx PCIe 硬核的器件，例如Virtex 5，Virtex 6，Spartan 6，并且实际在ML555 和ML605 开发板上实际测试通过。此外，驱动将板卡的控制封装起来，提供用户层简单的读写接口，方便上层程序的开发。-This document describes an approach bas
dds_key-feature
- dds key feature in this file i explain key feature of dds xilinx core.
ml605_MIG_pdf_xtp047_12.3
- xilinx mig totorial in vertix6
dds
- dds xilinx ip core for using
xtp038
- 关于xilinx的multiboot讲解-ABOUT multiboot of XILINX
xilinx_Timing_constraints
- Xilinx时序约束文档，包括什么情况下使用时序约束、为什么要时序约束、如何进行时序约束等。-Xilinx timing constraint document, including under what circumstances the use of timing constraints, why should the timing constraints, how to carry out the timing constraint.
Video_filterinf
- Project Report-Real-time User Adjustable Video Filtering create an embedded system that demonstrates real-time video filtering using a Xilinx Virtex II multimedia board
Real-time User Adjustable Video Filtering
- Real-time User Adjustable Video Filtering aim is to create an embedded system that demonstrates real-time video filtering using a Xilinx Virtex II multimedia board
12_Lab3
- practical example using verilog and vhdl by xilinx
LFSR
- practical example using verilog and vhdl by xilinx
DEMUX
- practical example using verilog and vhdl by xilinx