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verilog 七分频
- 用Verilog巧妙实现奇数分频电路的硬件描述
半整数分频器的实现（verilog）
- 半整数分频器的实现（verilog），本文以6.5分频为例！很实用的！,fen pin qi
50M
- verilog 语言写的分频模块，实现用50Mhz的时钟频率分出1hz的频率，也就是一秒的频率-verilog language sub-frequency module, using the 50Mhz clock frequency 1hz separation, that is, the frequency of second
miaobiao
- verilog写的分频程序,可以对输入的频率分频-Verilog write the sub-frequency procedures, can the frequency of the input frequency
Verilog--shiyanbaogao
- 有实验结果,用MOSIN6编写的,是Verilog HDL语言实现的. 练习三 利用条件语句实现计数分频时序电路 实验目的： 1. 掌握条件语句在简单时序模块设计中的使用； 2. 学习在Verilog模块中应用计数器； 3. 学习测试模块的编写、综合和不同层次的仿真。 练习四 阻塞赋值与非阻塞赋值的区别 实验目的： 1． 通过实验，掌握阻塞赋值与非阻塞赋值的概念和区别； 2． 了解阻塞赋值与非阻塞赋值的不同使用场合； 3． 学习测试模块的编写、综合和不同层
n_evendivider
- 标签： Verilog 分频器 N倍奇数分频器.(Verilog) N_odd_divider.v / Verilog module N_odd_divider (-Labels: Verilog divider divider N odd times. (Verilog) N_odd_divider.v/Verilog module N_odd_divider (
quartus-work
- 基于FPGA的VERILOG的分频器的设计，10分频设计的源代码和设计思路-Based od FPGA
verilogfenpinqi
- verilog分频器代码 分为偶数倍分频和奇数倍分频两个verilog源文件 附带一个说明文档-divider verilog code for multiple sub-divided into even and odd frequency divider several times with a two verilog source files documentation
div
- verilog任意分频电路实现，仿真效果非常好-div dclk
divide
- 关于verilog的分频程序 等占空比 非等占空比 小数分频 奇数分频-Verilog frequency on the sub-procedures such as the duty cycle of non-duty-cycle fractional odd frequency, etc.
onesecond
- 用verilog实现将50M晶振分频，得到1M的功能，本人已经用Quarter9.0运行成功。-To achieve with verilog 50M crystal frequency, get 1M' s functions, I have run successfully with Quarter9.0.
dividerverilogdesign
- verilog 分频器设计 偶数分频器和奇数分频器-divider verilog design even and odd divider divider
dir3
- VERILOG 语言写的使用状态机实现奇数分频-VERILOG language is written by the state machine to implement an odd number of points frequency
decimal_divison
- 使用双模计数器实现的FPGA小数分频器，语言verilog HDL。-FPGA implementation using dual-mode fractional divider counter, language verilog HDL.
verilog--divide-programs
- verilog任意分频程序，包括奇数倍分频和偶数倍分频，占空比为50 ，QuartusII上验证程序有效-verilog every divide programs, including an odd multiple divider and even multiple frequency, duty cycle 50 , the QuartusII on the verification process
random frenquency division
- verilog任意分频代码，作为新思路参考(veriliog code used as reference to new idea)
fenpin
- 可以实现n+0.5倍的分频，本程序是利用50MHz的FPGA开发板实现分别实现10MHz，2.5MHz的分频时钟。(N+0.5 times can be achieved frequency division, this procedure is to use 50MHz FPGA development board to achieve, respectively, 10MHz, 2.5MHz frequency division clock.)
encoder_clk
- 精确实现奇数分频，将FPGA开发板提供的25MHZ时钟分频为1MHZ，内含测试文件(Accurate realization of odd frequency division, the FPGA development board provides 25MHZ clock frequency divided into 1MHZ, containing test files)
FPGA分频
- xilinx spant6 PLL分频，生成4个不同频率的时钟，实现LED闪烁。(xilinx spant6 PLL frequency division)
Lesson07：BJ-EPM240学习板实验1——分频计数实验
- Quartus的分频计数试验视频讲解,讲解的很详细，对于新手来说还是蛮不错的(Quartus_frequency division technology test video explanation)