搜索资源列表
single_cycle_cpu
- 单周期CPU，实现十六条指令，结果数据写回寄存器组-Single-cycle CPU, achieving 16 instructions, the resulting data to write back to register file
CPU
- 用VC++模拟单周期cpu，是体系结构课程的一次作业，包括硬件设计，指令设计等，仅十几条汇编指令啦，程序还支持堆栈操作，能进行算术运算，输入运算表达式就能自动生成汇编代码，代码装载后可以调试运行，支持单步和全速运行-Using VC++ simulation of single-cycle cpu, is a one-stop course architecture, including hardware design, instruction design, only dozens of as
cpu
- 基于VHDL的单周期cpu开发，网上找的-cpu design
danzhouqiCPU
- VHDL单周期CPU设计,基于Quartus II 开发平台-VHDL single-cycle CPU design, Quartus II development platform based on
cpu
- 用Verilog语言编写的单周期cpu，实现的指令有 add,addu,addi,addiu,sub,subu,clo,clz,xori,nor,slt,slti,sltu,sltiu,blez,j.-Verilog languages ??with single-cycle cpu, implementation instructions are add, addu, addi, addiu, sub, subu, clo, clz, xori, nor, slt, slti, sltu,
mips-cpu
- 单周期的mips处理器设计，用vhdl语言实现各个模块的功能-Single-cycle mips processor design, using vhdl language functions of each module
CPU-source-code
- CPU设计代码，包括单周期CPU，多周期CPU，流水线CPU及相关ALU组件。-CPU design code, including single-cycle CPU, multi-cycle CPU, ALU pipeline CPU and related components.
cpu
- 这是一个quartus语言编写的单周期cpu，可以进行运算、存储等功能。-This is a quartus language of single-cycle CPU, computing, storage and other functions.
CPU
- 16位单周期CPU设计 重庆大学 计算机组成原理项目-16 single-cycle CPU design Chongqing University of Computer Composition Principle Project
CPU
- 31条指令单周期cpu，指令内容见pdf文件-31 single-cycle instruction CPU
cpu
- 单周期CPU，实现了部分简单指令，仿真模拟确认可行-Single-cycle CPU, to achieve some simple instruction, simulation confirm feasible
CPU(4)
- 基于ISE XILINX14.7开发的单周期CPU的基础指令实现代码 VERILOG-VERILOG implementation code base based on single-cycle instruction CPU ISE XILINX14.7 development of
CPU-master
- 单周期CPU的Verilog源码实现，基于Vivado(Single cycle CPU Verilog source code implementation, based on Vivado)
cpu
- logisim单周期cpu搭建，emmm 北航的 计算机组成(Single cycle CPU construction)
Single_cpu
- 单周期CPU自己课程大作业做的，亲测好用，verilog语言，适用vivado(Single cycle CPU course to do, pro - use, Verilog language, suitable for vivado)
单周期cpu设计
- 此为32位单周期MIPScpu的基于modelsim的源码设计，整个实现了R型指令和I型指令，完成了整个单周期cpu的设计
Verilog_Single_Cycle_CPU_check
- 用verilog写的一个单周期cpu，用于计组实验(A single cycle CPU written in Verilog for group experiment.)
CPU
- 北航 P3 单周期 Logisim分析图 支持通过强测 查重后果自负(BUAA P3 Logisim anality)
单周期CPU实验报告
- 单周期CPU的设计思路(包含数据通路、指令集、信号的设计)(Design Ideas of Single Cycle CPU)
单周期CPU大作业-2020
- Verilog projects cpu