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用一位全加器组成四位全加器
- 用一位全加器组成四位全加器. 所用语言是Verilog HDL. 主要用在加法器的设计中。-All-Canadian with a composed four-adder. The language used is the Verilog HDL. In addition main The design.
adder4_1
- 这是用vhdl编写的四位加法器，请多指教-this is the preparation of the four VHDL Adder, please enlighten
jiafaqi
- 实现四位加法器的VHDL代码，里面含有全加器的代码-achieve four Adder VHDL code, which contains the full adder code
adder_4bit
- 四位加法器，用OrCAD完成，可用于八位乃至十六位加法器的设计原型-four adder with OrCAD completed, can be used for eight or even 16 Adder design prototype
VHDL_add_4
- 本程序完成带进位输入输出的四位二进制加法运算，编程思想采用真值表转换成布尔方程式，利用循环语句将一位全加器编为四位加法器。
eecadd_8
- 此程序用VHDL语言编写，在四位加法器基础上完成8位二进制加法，输出是BCD码
eda四位加法器
- eda四位加法器
add4
- 一个四位加法器的VHDL语言实现，并通过编译测试-A four-adder realization of the VHDL language, and compile test
4bit_buma_adder
- Verilog作业 ：自己写的源码输入，补码输出的，由状态机控制的四位加法器，为保证时序，加法器模块为超前近位加法器，包含测试台，通过 Modelsim 、Synplify仿真。-Verilog operation: the source code to write their own input, complementary code output by the state machine to control the four adder, in order to ensure timing
adder17
- 实现17位加法，利用一个16位超前进位加法器和一个一位全加器构成的一个有进位输入和进位输出的17加法器，并且16位加法器利用的使四位超前进位加法器构成。它在booth乘法器设计中经常用到。可以使初学者对模块的调用了解更加透彻。-Adder 17 to achieve the use of a 16-bit CLA, and a one-bit full adder composed of a binary input and binary output of the adder 17, and
adder4
- 四位加法器，适合初学者学习使用，包括实验要求，四位加法器程序代码，QuartusII功能仿真后的波形图。-Four adder, suitable for beginners learning to use, including the experimental requirements, the four code adder, QuartusII functional simulation of the wave after.
chapter7
- VHDL 四位加法器 利用quartus II开发四位加法器，-VHDL comptur comparator_4
adder_4
- 详细介绍了四位加法器的verilog代码，还包括详细的testbench代码。-Details of the four adder verilog code, also includes detailed testbench code.
mux4
- 基于VHDL的四位加法器的实现，通过此加法器的设计，可以扩展到更多位的加法器的设计-VHDL-based implementation of the four adder, through the design of this adder, can be extended to more bits Adder
adder4
- 这是一个用verilog编写的四位加法器，编程环境是xilinx ise10.1.-This is a written with the four adder verilog, programming environment is xilinx ise10.1.
addandcount
- 四位加法器和计数器，采用Tanner设计，包括电路图，仿真和版图。-Four adders and counters, the use of Tanner design, including schematic, simulation and layout.
adder
- 通过四个半加器的互联，来实现四位加法器的电路结构-Through the interconnection of four and a half adder to achieve the four adder circuit
adder
- 实现四位加法器，适合初学者学习VHDL语言(it's an addler of four bits which is designed for the new designer of VHDL)
基于FPGA的四位加法器
- 基于FPGA的四位加法器verilog语言代码(be basaed upon FPGA adder4)
si四位加法器
- 内含三个普通的四位加法器，adder，adder4-2，adder4-3(library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity full_adder is port( a,b,ci :in std_logic; s,co :out std_logic); end entity; architecture rtl of full_adder is begin s&