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- Actel 基本VHDl模块源代码，包括BCD、LCD、PLL等-Actel basic VHDL source code modules, including BCD, LCD, PLL, etc.
Static_PLL
- 静态pll实验程序，在actel的fusion系列FPGA中综合通过-Pll static experimental procedures, the fusion line in the Actel FPGA integrated through
Static-PLL
- 基于Actel开发平台的静态锁相环设计，verilog实现-Actel development platform based on the static PLL design, verilog realized