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std_ovl_v2p7_Feb2013
- 目前最新的OVL库，里面是标准的ASSERTION模块，支持VHDL刚Verilog，最近在做AXI协议验证的时候用到，分享下-The latest OVL(open verification library),including all standard module of assertions(VHDL and Verilog). It can be used into AXI Protocl Verification. Just share with you guys.
AXI_Master_FSM
- AXI Master, is implement with FSM
ZedBoard-step2
- ZedBoard学习手记（二） 开发自定义AXI总线外设IP核——以LED和开关为例 -ZedBoard learning s note (2) develop a custom AXI bus peripherals for leds and switch IP core- for example
axi_slave
- AMBA axi利用verilog搭建的axi_slave模块-AMBA axi use verilog module built axi_slave
axi_bfm_ug_examples.tar
- axi_bfm_ug_examples axi bus function model user guide examples-axi_bfm_ug_examples axi bus function model user guide examples
lab1
- AXI-Lite bus with SPI on System C
shruthi-proj
- The APB is part of the AMBA 3 protocol family. It provides a low-cost interface that is optimized for minimal power consumption and reduced interface complexity. The APB interfaces to any peripherals that are low-bandwidth and do not require the high
AMBA_v30_AXI_v10
- ARM AMBA AXI Protocol guide
axi_master_latest.tar
- axi 总线 设计 和 仿真， 可以在设计中直接运动， 提供完整源代码和仿真文件， 用vhdl 语言实现。-axi bus design and simulation, you can directly exercise in design, providing full source code and simulation files, using vhdl language.
8_LCD-TEST_ok
- ‧ (1) 點時脈（DCLK 信號） –DCLK 是整個LCD 工作的基礎。它提供LCD工作的基本時脈。基本 的公式為：DCLK = (HCLK)/((CLKDIV+1)*2) –其中HCLK 是AXI/AHB時脈，CLKDIV 是在LCD 控制暫存器1。 ‧ (2) 水平同步（HSNYC信號） –該信號提供水平方向的圖像同步。該信號出錯會導致輸出水平方 向的問題。 ‧ (3) 水平前廊（HFPD信號） –該信號協助提供水平方向的圖像
xilinx_axienet_mdio
- MDIO bus driver for the Xilinx Axi Ethernet device.
llcp
- mmp AXI peripharal clock operation source file.
axi_master
- 自己写的 AXI master code-AXI master code
AXI_slave
- 自己写的 AXI slave 代码，是ARM 内嵌的 总线通信-AXI slave code
of_xilinx_wdt
- Watchdog Device Driver for Xilinx axi xps_timebase_wdt.
adi-axi-spdif-tx
- partial power down enable for Linux v2.13.6.
axi_dispctrl
- zynq AXI display controller source for zybo
xilinx_can
- Xilinx Axi CAN Zynq CANPS controller Device Tree Bindings.
axis_fifo
- VIVADO下使用verilog编码的axi fifo的简单使用，仿真通过，供初学者学习。-Use the following VIVADO verilog coding axi fifo simple to use, through simulation, for beginners to learn.
AXI_VIP
- axi vip code used in almost all the interface projects in the soc and verification environments in arm processors