搜索资源列表
Plasticidad
- UMAT, FOR ABAQUS/STANDARD INCORPORATING ELASTIC-PLASTIC LINEAR ISOTROPIC HARDENING. LARGE DEFORMATION FORMULATION FOR PLANE STRAIN AND AXI-SYMMETRIC ELEMENTS. IMPLICIT INTEGRATION WITH CONSISTENT JACOBIAN-UMAT, FOR ABAQUS/STANDARD INCORPORATING ELAST
ds669-axi-interface-kc705-microblaze-processor.pd
- KC705 Embedded Kit full datasheet
axez_v4.0
- 阿西文章管理系统V4.0 新增功能: 进一步优化首页及文章页面，新增了搜索功能。 蜘蛛爬行记录新增了SOSO图片蜘蛛及百度图片蜘蛛的抓取记录！ -Axi article management system V4.0 new features: to further optimize the home page and article page, the new search function. Spider crawl records added spider images and spider
axi_jesd204b
- ADI JESD204接口的ADC与Xilinx FPGA接口IP，包含Verilog和VHDL源代码，AXI总线接口，ADC串行控制接口-ADI IP for interfacing JESD204 ADC to Xilinx FPGA, include Verilog/VHDL source code, AXI interface and serial config interface
cmos_in_axi4s_v1_0
- camera parallel interface to axi stream interface source code
uvm_axi-master
- axi uvm vip, verification model -axi system verilog
Assignment-02-1
- this all about viviado AXI four light bus communication. it is good for every one who is intersted in studying vivado axi light interfacing-this is all about viviado AXI four light bus communication. it is good for every one who is intersted in study
AMBA
- SPECS RELATED ABOUT THE AMBA AXI
axi_dma_test
- zynq 开发板 axi dma功能测试(zynq borad axi dma function test)
XPS_Custom_IP_Tutorial
- Tutorial to create a custom AXI based IP for Xilinx
CV_FPGA_to_HPS_Bridge_Design_Example
- FPGA通过AXI总线传输数据给ARM,ARM使用DMA方式接收数据！(FPGA to ARM Bridge design example)
xilinx_axidma-master
- xilinx axi dma driver
gpio_axi
- Zturn board - GPIO - AXI
arm_amba_reference_manual.tar
- ARM AMBA REFERENCE MANUAL! 2011 YEAR
AXI4与AXI3的区别
- AXI4与AXI3的区别,l例如：AXI4对burst length进行了扩展：AXI3最大burst length是16 beats,而AXI4支持最大到256 beats，但是仅支持INCR burst type超过16 beats，exclusive access也不能超过16beats;。(the different of AXI4 and AXI3)
axi_master_latest.tar
- AXI_Master_verilog_code
axi_ad9361
- AXI_AD9361 的 verilog 驱动工程，包含数据接收，数据发送 AXI总线 ，全部是verliog实现(AXI_AD9361's Verilog drive project, including data reception, data transmission AXI bus, all verliog implementation)
cpu_uart_leds_ip
- 基于Altera 的一个IP核，能完成串口收发,以及自定义IP,可以作为自定义AXI总线接口的例子(Based on Altera's IP core, to complete the serial transceiver, as well as custom IP, as a custom AXI bus interface example)
src
- 基于AXI 总线的可配置脉冲计数器，可以配置计算脉冲的个数。(The configurable pulse counter based on AXI bus can be configured to calculate the number of pulses)
zynq_dma_test
- pl dma 驱动, 自测试文件，需要将两端stream对接即可(pl AXI dma driver, In block design , connect mm2s with s2mm.)