卷积神经网络实现的参考,借助于英伟达的开源硬件加速器。(Convolutional neural network reference, with open source hardware accelerator in nvidia.)

THU微纳电子系ic设计课程大作业，使用verilog实现CNN加速器，含一层卷积和池化，仿真通过。(a CNN accelerator written in VerilogHDL, including one conv layer and one pooling layer, simulation passed)

基于FPGA的CNN加速器，极大的提高了FPGA的速度和性能，同时减小了功率。