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de2_clock
- 适合DE2板，能够在板子上的液晶显示器上实现时钟功能。-for Dictyophora board, in the way of achieving LCD clock function.
part2
- Implement a 3-digit BCD counter. Display the contents of the counter on the 7-segment displays, HEX2− 0. Derive a control signal, from the 50-MHz clock signal provided on the DE2 board, to increment the contents of the counter at one-se
clock-a-stopwatch
- 基于DE2-70平台，可实现功能： 1、在LCD上显示时间 2、在数码管上显示跑表-DE2-70-based platform, enabling functions: 1、display time on the LCD 2、display stopwatch the digital tube
zhaowan.clock
- clock,可以在quarter上运行，de2开发平台-clock, in the quarter to run, de2 Development Platform
clock
- 这是一个数字时钟的数字逻辑电路，整个工程打包上传，时钟可以计时、校时、整点报时、定时闹钟。使用电路图实现的。在quatarsII里面仿真的并且下载到DE2板上运行过。-This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clo
Clock_Full
- clock program on altera de2-70 board
A9
- clock divider, has multiple versions of clock divider for the de2 board
FPGA-clock
- 基于VHDL的时钟设计（de2开发平台），内含源代码，各模块的时序仿真图，结构原理图，以及完成报告。供大家参考学习。-VHDL-based clock design (de2 development platform), contains the source code, simulation charts of each module, structure diagram, and the mission report. For reference study.
DigitalWatch
- Digital watch write in Verilog HDL language simulate the real clock in Atera DE2 development board
VGA2
- VGA controller initialy designed for altera DE2 FPGA with 10 bits DAC. probably works with other systems if you have the correct clock source.
clock
- 用VC编写的一个万年历~在DE2开发板上直接可以运行~-Prepared using a calendar ~ VC DE2 development board directly in the run ~
dianziqin
- VHDL语言编写的可以显示时钟的电子琴，使用Quatrus II开发，实验板为DE2-VHDL language keyboard that can display the clock, using Quatrus II development, test board for the DE2
Digital-clock
- 数字钟工程，用QuartuesII软件开发的，在DE2-70上运行成功，可以直接使用，计时准确，文件代码简单，适合初学者借鉴。-Digital clock project, using QuartuesII software development, running on the DE2-70 success, can be used directly, accurate timing, file the code is simple, suitable for beginners learn
clock_1Hz
- Clock 1Hz with duty cycle control for verilog for DE2-115 Altera FPGA
szsz
- 在DE2实验箱上实现数字时钟功能 包括了秒、分、时的基本显示功能-Implemented on the DE2 kit features include a digital clock seconds, minutes, when the basic display
timer
- 用verilog 实现时钟的功能，并在DE2开发板上调试-Clock with verilog and debug on the DE2 board
clocker-and-timer
- 时钟与计时器，FPGA实验alter DE2开发板自带光盘的案例教程编程解析-Clock and timer, FPGA experimental alter the DE2 development board comes with the CD case tutorial programming resolution
clock
- 数字时钟led显示，de2开发板，HEX显示分秒-digital clock
clock
- there's a clock divider for DE2 altra board clock (50MHz)
电子时钟
- 基于DE2-115的数字时钟 1.液晶显示，数码管显示 2.整点报时 3.闹钟 4.设置时间 5.设置闹钟(Digital clock based on DE2-115 1. LCD display, digital tube display 2. whole point 3. alarm clock 4. setting time 5. set the alarm clock)