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stopwatch
- 利用Quarteus II 6.0 设计一个秒表，通过7段数码管显示，以及开关控制秒表的启停。-Quarteus II 6.0 design using a stopwatch, digital tube through 7 show, as well as the switch control of the start and stop the stopwatch.
paobiao
- 给出了数字跑表的源代码，设计了分频模块，实现了真实的时间计数，通过这个工程的训练，能更好的了解Quartus II数字电路开发的过程。-Digital stopwatch given the source code, design the sub-frequency module, the realization of the true count of time, through this project the training, to better understand the Quart
clock
- 用verilog实现的数字跑表，下载到FPGA开发板上验证通过。下载后从新分配引脚即可用。-Verilog implementation using digital stopwatch, download to FPGA development board to verify the adoption. After the download you can use the new distribution of pins.
paobiao
- 一个基于FPGA的数字跑表系统的设计，最小单位是百分表位。采用十进制进位。-FPGA-based digital stopwatch system design, the smallest unit is a digital dial indicator. Binary using the metric system.
DigitalWatchVerilog
- 一个用Verilog实现的数字跑表的程序 希望对你的设计有帮助-With the realization of a digital stopwatch Verilog process of design you would like to help
stopwatch
- 基于vhdl的数字秒表，计时精度为1/100秒，最长计时时间为59分59.59秒；设有复位开关、起停开关；验证可用。-On vhdl digital stopwatch, timing accuracy of 1/100 seconds, the longest time time of 59 minutes 59.59 seconds with reset switch, start-stop switches validation is available.
paobiao
- 基于Verilog HDL的完整数字跑表工程，在试验机台上运行验证通过了的。 用8位7段数码管分别显示微妙，秒，分。 有开始，暂停，复位功能。 学习VerilogHDL的经典例子，添加了显示功能。-Complete Verilog HDL-based digital stopwatch works in the test machine is running verify pass the platform. With 8-bit 7-segment digital tube sho
StopWatch
- digital stop watch using avr atmega8
stopwatch
- 数字秒表的VHDL代码。当设计文件加载到目标器件后，设计的数字秒表从00-00-00开始计秒。，直到按下停止按键（按键开关S2）。数码管停止计秒。按下开始按键（按键开关S1），数码管继续进行计秒。按下复位按键（核心板上复位键）秒表从00-00-00重新开始计秒。-The VHDL code for digital stopwatch. When the design document loaded into the target device, the designed digital stop
code
- 这是一个数字跑表的代码，用FPGA实现的，对大家或许有用-This is a digital stopwatch in the code, FPGA implementation, perhaps all of us
Stopwatch
- Code for a simple digital stopwatch using At89C51 microcontroller. The stopwatch counts from 0 to 9 seconds.The code is written in Assembly language.
digital-clock-
- 本代码采用verilog HDL语言编写。实现的是数字跑表计时功能-The code using verilog HDL language. Implementation is a digital stopwatch timer functions
Two-digital-stopwatch-
- 二位数字秒表 具有记时，开始，暂停，结束，清零，功能。-Two digital stopwatch has in mind, start, pause, end, clear, functional.
Digital-stopwatch-schematic
- 数字式秒表原理图及仿真波形，真实反映数字秒表内部结构-Digital stopwatch schematic and simulation waveforms, a true reflection of the internal structure of digital stopwatch. . .
Stopwatch
- 89c52定时器中断动态扫描数码管实现秒表-89c52 timer interrupts to achieve dynamic scan digital stopwatch
Digital-stopwatch-design
- 数字秒表的设计报告，用VHDL语言编写程序，实现分析讨论中各种功能，分别进行编译并生成相应的模块，然后将这些模块连接起来形成电路图，并进行编译、仿真。-Digital stopwatch design reports, using VHDL language programming, analysis and discussion of various functions to achieve, respectively, to compile and generate the correspo
Digital-stopwatch
- 数字秒表，用VHDL语言描述，用层次设计概念，将设计任务分成七个子模块，规定每一模块的功能和各模块之间的接口，然后再将各模块合起来形成顶层文件联试。-Digital stopwatch, using VHDL descr iption, level design concept, the design task is divided into seven sub-module to provide the interface between each module functions and m
8-bit-digital-stopwatch-program
- 里面有用C语言编辑的适用于单片机开发的8位数码管秒表程序，前四位显示秒，后四位小时毫秒。- suitable for microcontroller development of the 8-bit digital stopwatch program
Digital-stopwatch
- 1、了解数字秒表的工作原理。 2、进一步熟悉用VHDL语言编写驱动七段码管显示的代码。 3、掌握VHDL编写中的一些小技巧。 -1, to understand the working principle of digital stopwatch. 2, more familiar with the use of VHDL language driver seven segment display code. 3, master VHDL prepared some of the t
Digital-Stopwatch
- 利用单片机及数码管，设计一个两位数的数码秒表，能够暂停以及清零操作-And the use of single-chip digital control, the design of a two-digit digital stopwatch, the ability to pause and clear operation