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pipelined-mips-cpu
- 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
mips
- 在maxplus上实现了一个5级流水线的mips cpu，含cache-In maxplus to achieve a 5-stage pipeline of the mips cpu, with cache
cpu
- 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
CPUsourcecode
- 本设计实现了一个具有标准的32位5级流水线架构的MIPS指令兼容CPU系统。具备常用的五十余条指令，解决了大部分数据相关，结构相关，乘除法的流水化处理等问题，并实现了可屏蔽的中断网络。-This design implements a standard 32-bit 5-stage pipeline architecture of MIPS instruction compatible CPU system. Instructions with more than 50 commonly use
instruction_decode_v
- MIPS 5 stage pipeline, this file is for instruction decode. you can use it to place in pipline. this has been used in a study lab.
spim-8.0
- 一个模拟MIPS结构cpu的程序，完成cpu的基本功能，用于模拟5级流水cpu-Structure of a simulated MIPS cpu' s program, complete the basic functions of the cpu, used to simulate the 5-stage pipeline cpu,
Pipelined-MIPS
- MIPS架构5级流水线设计，支持常用的整数指令。-5-stage pipeline MIPS architecture designed to support common integer instructions.
MIPS_Pipelined_CPU
- MIPS Pipelined CPU written on VHDL with commands, 5 stage pipeline
pipelined-mips-cpu-master
- misp 5 stage pipeline
h.Mohseni_pipe_line
- mips processor 5 stage pipeline
MIPS
- 5个stage的pipeline MIPS，支持着JUMP，BRANCH等跳转命令。-simple 5-stages MIPS structure which supports forwarding commands.