大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等，此原码基于长江大学可编程器件实验箱,如要运行在其他平台上需要重新定义管脚-University VHDL language experiment Daquan, based on the max-plus2 platform within 8-3 decoder, 8 Adder, digital clock, digital d

RS编译码器的DSP实现，首先用MATLAB仿真，最后在DSP上实现-RS of DSP codecs to achieve, the first simulation using MATLAB, and finally realized in the DSP

内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等-There are 8-3 decoder, 8-bit adder, digital clock, digital display, 74ls138, 8,4 bit counter, d, rs flip-flops, adders, traffic lights, etc.