搜索资源列表
spi
- SPI master的verilog代码-Verilog code for SPI master
SPI_TEST
- The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave d
FPGASPI
- 用FPGA实现主SPI程序,包含开发工程、测试文件和源文件代码-fpga design the SPI code
AIC
- 使用FPGA/CPLD设置语音AD、DA转换芯片AIC23，FPGA/CPLD系统时钟为24.576MHz 1、AIC系统时钟为12.288MHz，SPI时钟为6.144MHz 2、AIC处于主控模式 3、input bit length 16bit output bit length 16bit MSB first 4、帧同步在96KHz-The use of FPGA/CPLD set voice AD, DA conversion chip AIC23, FPGA/
spi.tar
- This is a verilog code used oversampled clock to implement SPI slave. Also include C code for a ARM processor as the SPI master-This is a verilog code used oversampled clock to implement SPI slave
spi_master_control
- VHDL SPI 控制器FPGA官网提供-VHDL SPI controller FPGA to provide official website
spi_master
- SPI wishbone master and verification environment
spi_core_open
- SPI 设计 为主机设计，供大家参考,希望对大家有用-SPI master design
spi_master
- SPI接口的实现以及对外设的读写操作，其中包扩了几种工作方式，同时可以读取外设的版本号，传输速率可以达到2Mbps-SPI interface implementation, as well as read and write operations on the peripheral, which extended several work packages at the same time can read the version number of peripherals, transfer
spi_verilog
- 实现SPI MASTER功能，并有仿真代码和仿真结果。-To achieve SPI MASTER function, and a simulation code and simulation results.
conjoined
- SPI protocol: Serial Periphral Interface with both slave and master incorporated-SPI protocol: Serial Periphral Interface with both slave and master incorporated
l1ghVhVI
- The VSPI core implements an SPI interface compatible with the many -- serial EEPROMs, and microcontrollers. The VSPI core is typically used -- as an SPI master, but it can be configured as an SPI slave as well.
SpiMaster
- This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile an
SPI-Master-Core-DAC-ADC-spartan
- SPI Master Core for spartan (ADC, DAC) vhdl code
SPI-Core_nguyen
- SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE
SPI-master-P-tb
- SPI master VHDL realisation Also contains TestBench
spi_mem_programmer-master
- spi_mem_programmer A simple verilog module for programming (Q)SPI flash memories
verilog_spi-master
- verilog_spi A simple demo SPI interface implemented in verilog
SPI
- 使用VHDL写的SPI Master模块(Using the SPI Master module written in VHDL)
spi
- 利用VHDL在FPGA内实现SPI总线的主从控制器设计(SPI Master and Slave Controller)