搜索资源列表
Example-s5-1
- “\Example-s5-1\des” 目录下为设计工程，其设计输入采用Synplify预先编译好的.vqm网表 “\Example-s5-1\source”目录下为设计的源代码，这里只给出了Verilog语言实例，仅供读者参考 “\Example-s5-1\source \area_opt”目录下为面积优化的代码 “\Example-s5-1\source \perf_opt”目录下为性能优化的代码 “\Examp
huawei
- 华为内部资料，包括verilog电路设计，硬件工程师手册，verilog约束，synplify使用指南等。内容较全面。-Huawei internal information, including verilog circuit design, hardware engineers manual, verilog constraints, synplify use guides. Content more comprehensive.
gsm_ddc
- 基于GSM的数字下变频代码，能够直接生成Verilog代码，需要Synplify DSP 支持。-GSM DDC code. This Model can directly generate RTL code via Synplify DSP.
BPSK_receiver
- BPSK接收机设计，能够通过Synplify DSP直接生成Verilog代码。-BPSK Reciver model. This simulink model can generate RTL code via Synplify DSP.
ChannelizerFFT
- FFT 模型，能够演示多通道FFT的实现过程。-FFT Multi-channel model. This simulink model can generate RTL code via Synplify DSP.
dct2d
- 2D-DCT, 二维离散余弦变换模型。能够通过Synplify DSP生成Verilog代码 -2D-DCT model. This simulink model can generate RTL code via Synplify DSP.
synplify-ISE-ModelSim
- 关于FPGA的仿真文档，使用synoplify，ise和modelsim三者联合仿真，适合初学者入门-FPGA on the simulation of the document, the use of synoplify, ise and modelsim co-simulation, suitable for beginners entry
wp386_Hierarchical_Design_Synopsys_Xilinx
- Hierarchical Design Synopsys Xilinx with Synplify tool