搜索资源列表
BASE-T0-VHDL-DSP
- 基于VHDL的FSK信号的调制与解调算法实现
DSP例子
- DSP builder samples
FIFO_EMIF.rar
- 实现FPGA通过EMIF总线给DSP定期发送数据的功能,FPGA implementation through the EMIF bus regularly send data to the DSP function
CIC_deci4.rar
- cic抽取滤波器ip核，用于射频采样数字下变频模块的核心数字信号处理部分.此ip核已经过ise10.2验证,CIC decimation by 4 filter，used in Direct RF sampling of GPS signal. the core dsp block in a frondend design
EnDatlightversion
- 海德汉绝对值编码器的ENDAT2.2协议代码，用于编码器数据的解码，然后把得到的数据传送给DSP处理，我们公司用于高精度伺服驱动器上。-Heidenhain encoder absolute agreement ENDAT2.2 code encoder data for decoding the data and then transmitted to the DSP processing, our company for high-precision servo drive.
IIR
- 利用dsp builder设计的IIR滤波器，已经验证完全可以使用，只需要把其中系数改变。内含VHDL代码-Design IIR filters by dsp builder have been verified , just change the coffetions including VHDL code.
DSPBuilderreferencemanual
- DSP Builder 参考手册,主要用于simulink实现算法后，可将其自动转换为vhdl语言应用。-DSP Builder Reference Manual, mainly for simulink algorithm may be automatically converted to VHDL language applications.
DSP_design_based_on_FPGA
- 用FPGA设计DSP,2007年上海FPGA高级研修班清华博士贺光辉讲义-FPGA Design with DSP, 2007 in Shanghai FPGA advanced training classes Tsinghua notes Dr. He Guanghui
write_io
- DSP EMIF 扩展io程序 DSP EMIF 扩展io程序-DSP EMIF procedures to expand io expansion io procedures DSP EMIF
DDC_CIC
- 用CIC 和 FIR Filters设计的数字下变频器，DSP Builder6.1版工程文件-Using CIC and FIR Filters Design of Digital Down Converter, DSP Builder6.1 version of project file
VLSIFFTRadix2forDSP
- VLSI implementation of high speed and high resolution FFT algorithm based on Radix 2 for DSP application
80sp1_DSP
- Altera 的DSP Builder 8.0的破解文件-Crack files for dsp builder 8.0
FPGADSPBuilder
- DE2平台应用及DSPBUILDER技术，是altera杯上海交大电子设计竞赛内部材料，内含详细设计原理及源代码-DE2 platform and DSP BUILDER technology, Shanghai Jiaotong University altera Cup Electronic Design Contest of internal materials, including the principle of the detailed design and source code
Xil3SD1800A_MIG_simplifiedUI_vlog_v92
- verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
6713_FPGA
- DSP+FPGA+USB2.0板子电路图 DSP是6713；FPGA是XilinxXC2S200；USB芯片是CY68013A-128AXC-DSP+ FPGA+ USB2.0 circuit board DSP is 6713 FPGA is XilinxXC2S200 USB chip is CY68013A-128AXC
dsk5509a_v1
- Sectrum DSP 公司开发的5509DSP开发板，相对于国内的SEED公司要强的多，里面包括全部的电器原理图，例程说明，测试程序源码。对于设计DSP硬件电路板有很大的帮助！-Sectrum DSP development board developed by 5509DSP, compared to domestic companies stronger multi-SEED, which includes all of the electrical schematics, routine
RISC-DSP
- RISC-DSP组合处理器设计优化[1].-RISC-DSP processor design portfolio optimization [1].
FPGA-DSP
- vhdl编写的FPGA与DSP接口程序，在FPGA内分配了两块双BUFFER与DSP进行通信-vhdl prepared FPGA and DSP interface program, the FPGA within the allocated 2 pairs of BUFFER to communicate with the DSP
3813412-Matlab-Simulink-Simulink-Matlab-to-Vhdl.r
- Simulink/Matlab-to-VHDL Route for Full-Custom/FPGA Rapid Prototyping of DSP Algorithms
VHDL-FIR-filters
- ynthesizable FIR filters in VHDL with a focus on optimal mapping to Xilinx DSP slices. This repository contains a transposed direct form, systolic form for single-rate FIR filters and a custom parallel polyphase FIR decimating filter. The VHDL has be