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verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器,verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum m
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运用Verilog 语言进行数字积分法，将X轴和Y轴进行插补运算。-Verilog language using digital integration method, the X axis and Y axis interpolation operations.
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插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现-Interpolation filter, audio decoder for modulation and demodulation, filter coefficient shift combined with the realization of
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线性插值算法,对高速二次线性插值算法的讨
论-Linear interpolation algorithm, the second high-speed linear interpolation algorithm discussion
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数控里的数字积分，微分插补。
DDA插补-NC integral to the figures, differential interpolation. DDA interpolation
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半带插值滤波器设计、综合、仿真和硬件测试-Half-band interpolation filter design, synthesis, simulation and hardware test
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在Quarues7.2下实现数字信号的正交相干检波的Bessel内插法-Quarues7.2 achieved in the digital signal of the quadrature coherent detection Bessel interpolation
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图形图像H264插值算法，应用于图像视频处理-H264 graphic image interpolation algorithm is applied to image video processing
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本代码设计的是一个通讯系统软件无线电中变换比为5/4的分数倍抽取器，用Verilog编程首先实现4倍内插，再实现5倍抽取。-The code design is a software-defined radio communication system in transformation ratio 5/4 points times the extractor, using Verilog programming the first to achieve four times the inter
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复杂的插值函数，用于颜色空间转换
verilog-The complex interpolation function for color space conversion verilog
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本程序为直线插补程序,运用在数控机床上.RAR-This procedure is linear interpolation procedure, used in CNC machine tools. RAR
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本设计主要用来进行图像采集处理，通过摄像头采集图像信息，经过插值算法后存储到外部SDRAM，然后读取图像数据，进行边缘滤波处理后经VGA输出到屏幕上。-This design is mainly used for image acquisition and processing,through the camera capture image information,after interpolation to the external memory after the SDRAM,and th
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CCD图像的颜色插值算法研究及其FPGA实现 ，这是一篇论文，里面详细介绍了如何实现图像处理的方法-CCD color image interpolation algorithm and its FPGA implementation, which is a paper, which details how to implement image processing method
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通过VHDL实现H.264算法中的半像素插值模块。该模块儿可在30个周期内完成一个4x4块的横纵斜插值。-H.264 algorithm by VHDL implementation of the half pixel interpolation module. The module can be in 30 children complete a cycle of vertical and horizontal 4x4 block Xiecha value.
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是用 vhdl 来实现数控中的数字积分法插补-Vhdl to the NC is the number of points in the interpolation method
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dda 插补法中 由vhdl 语言来实现-dda interpolation achieved by the vhdl language
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cic 滤波器，vhdl代码 ，内插与抽取-cic filter ，vhdl code about decination and interpolation
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4倍内插值的fir成型滤波器，语言vhdl，工程已建立，可以直接运行-4x interpolation of fir shaping filter, language vhdl, project has been established, you can directly run
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基于cpld 平台，VHDL语言编写，四轴两插补控制程序。包括单轴运动、两轴插补程序、CPLD与ARM通信程序。经过工程实践应用。-Based on the CPLD platform, VHDL language, four two axis interpolation control program. Including the single axis motion, two axis interpolation procedures, CPLD and ARM communication
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