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verilog-som
- 拿verilog编写的som(自适应神经网络算法)，用于障碍物检测，基于FPGA可综合实验，已经在altera的cylcone上实现-Canal verilog prepared som (adaptive neural network algorithm) for obstacle detection. Based on FPGA synthesis experiments, in altera achieve the cylcone
uart-verilog-vhdl
- 拿verilog和vhdl编写的串口通信代码(可综合)-with vhdl and verilog prepared by the serial communication code (synthesis)
djpeg_vlsi
- jpeg解码电路，是verilog编写的，可以综合，很有实用价值。-jpeg decoder circuit, is prepared verilog, synthesis, very practical value.
Verilog-Semantics
- Synthesizable Verilo---syntax and semantics一本很好的关于verilog可综合设计的参考书-Synthesizable Verilo --- syntax and semantics a good Verilog synthesis of the reference design
8051单片机源码verilog版本
- 8051单片机源码verilog版本 包括rtl， testbench， synthesis ,Verilog source code version of 8051, including rtl, testbench, synthesis
DDS
- DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序.-DDS program folder, complete direct digital frequency synthesis function, sine, triangle, square
ddrsdram_verilog
- 内附doc是DDR SDRAM 参考设计文档；model包含SDRAM Verilog的模型；simulation包含verilog测试平台、modelsim工程文、设计库函数；source包含verilog源文件；synthesis包含工程的综合文件 。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM Verilog model simulation with veri
Verilog编码与综合中的非阻塞性赋值CummingsSNUG2000S
- Verilog编码与综合中的非阻塞性赋值-Verilog code and synthesis must blocking evaluation
OVL
- OVL——基于断言的verilog验证 Verilog数字系统设计:RTL综合、测试平台与验证-OVL- assertion-based verification of Verilog Verilog digital system design: RTL synthesis, test and verification platform
hbf
- 半带插值滤波器设计、综合、仿真和硬件测试-Half-band interpolation filter design, synthesis, simulation and hardware test
HuaweiFPGAdesignflowguide
- 华为内部的FPGA设计培训教程，详细阐述了设计流程图、Verilog HDL设计、逻辑仿真、逻辑综合。对大家的学习一定有帮助的。-Huawei within the FPGA design training tutorial, a detailed flow chart of the design, Verilog HDL design, logic simulation, logic synthesis. Study of the U.S. must have help.
Verilog_NBA
- Verilog非阻塞赋值的仿真/综合问题-Non-blocking assignment Verilog simulation/synthesis
A_bit_serial_data_transmitter
- 比特序列传送模块 把输入的八位比特数据 做循环后每个比特输出 详细请看英文描述-• To create Verilog-HDL modules written in the RTL style appropriate for both simulation and synthesis, for the various component parts of an Asynchronous Serial Data Transmitter. • To verify th
TRL_Design_of_a_asynchronous_bit_serial_data_trans
- RTL 异步数据传送模块 用verilog HDL 语言描述 输入为八比特数据，执行操作后异步每比特输出。-• To create Verilog-HDL module written in the RTL style appropriate for both simulation and synthesis, for an Asynchronous Serial Data Transmitter. • To verify the correct behavi
VerilogHDL
- 入门级经典《Verilog HDL Synthesis A Practical Primer》中英文版，绝对的好书！！！ -classical book Verilog HDL Synthesis A Practical Primer
reedsolomon
- reed solomon encoder synthesis and simulation is done using verilog and working fine
mips
- 使用verilog設計的MIPS處理器，mips處理機的模擬且可合成驗証-MIPS processor using the verilog design, mips processor synthesis of analog and can be verified
Verilog_Digital_Design_Synthesis
- Verilog HDL A guide to Digital Design and Synthesis Samir Palnitkar SunSoft Press 1996
verilog-ieee.pdf.tar
- IEEE 2001 verilog 标准 ,详细讲述了 业内 公认的 VERILOG 标准 ,-The Verilog¤ Hardware Descr iption Language (Verilog HDL) became an IEEE standard in 1995 as IEEE Std 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstractio
ug901-vivado-synthesis-examples
- verilog edge detector codee, for vibado tollssssss