搜索资源列表
sWave.rar
- 正弦波，Verilog波形发生器，很好的东西,Sine wave, Verilog waveform generator, a good thing
EPM240_SCH_and_program.rar
- EPM240 cpld 原理图+程序。 Verilog HDL语言。 程序有正弦波发生器，ADC0804直流采样和显示，汉字滚动，交通灯，键盘，显示程序，计数器等等。,Schematic diagram+ EPM240 cpld procedures. Sine wave generator procedures, ADC0804 DC sampling and showed that Chinese scroll, traffic lights, keyboard, display pro
DDS-top.rar
- 能够基于DDS实现输出正弦波形的一部分程序，利用Verilog HDL语言编写。,Able to achieve based on the DDS output sine wave-shaped part of the procedure, the use of Verilog HDL language.
sin.rar
- 用Verilog语言在FPGA内实现一256个采样点的正弦波，已尝试，挺好用的~~~,Verilog language used in the FPGA to achieve one of the 256 sampling points sine wave, I have already tried it, very useful~ ~ ~
fifo
- 异步fifo，用Verilog编写，包含testbench，已经通过modelsim调试，内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave
DDS
- 我们小组共了一个月做的DDS,程序核心用的是Verilog HDL,有仿真波形,输出正弦波,方波,及三角波,步进可调.频率范围1HZ--10MHZ-Our group for a month to do a total of DDS, the procedure is used in the core of Verilog HDL, there are simulation waveform, the output sine wave, square wave and triangular wa
DDS
- DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序.-DDS program folder, complete direct digital frequency synthesis function, sine, triangle, square
FINALWORK
- 简易信号发生器 可产生正弦波、方波、三角波、锯齿波 周期可调 verilog-Simple signal generator can produce sine, square, triangle wave, sawtooth-cycle adjustable verilog
wm8731_zhengxianbo
- 讲诉了如何编写VERILOG程序通过DE2开发板的wm8731芯片产生正弦波-Talk about how to write VERILOG v. procedure DE2 development board wm8731 chip generated sine wave
SPWM
- VHDL采用自然采样法写的SPWM，里面有正弦表，可以通过外接输入正弦波和三角波的频率。 -VHDL using written natural sampling SPWM, there are sine table, you can enter through the external sinusoidal and triangular wave frequency.
sgs32
- Verlog HDL 写得一款32路方波发生器，例子是4路可以自己加，相位可调，频率可调，占空比可调。具体参见readme.doc.此处只提供了源码包含顶层模块sgs32.v 子模块dds.v和pll设置模块altp.v及波形驱动文件-Verlog HDL write a 32 square-wave generator, for example, is able to add 4-way, phase adjustable, adjustable frequency, adjustable d
WAVE
- 关于波形发生功能的Verilog代码和Quartus文件完整文档。-Waveform occurred on the function of Verilog code and Quartus files a complete document.
PWM
- 使用VERILOG 语言产生PWM波。只需要使用处理器或内核直接配置相应的寄存器就可以输出PWM波。-VERILOG language use PWM wave generated. Only need to use the processor or core directly corresponding configuration register can output PWM wave.
signal
- verilog写的串口控制信号发生器，能通过用串口控制产生正弦波方波等信号-written in verilog serial control signal generator, can be generated using serial control, such as sine wave square wave signals
dds_final
- 使用Verilog HDL语言实现的一个DDS，可以发生0-10Mhz正弦波、方波、三角波，频率步进可调，FM调制、AM调制，调制度可调。DA芯片为8位并行，160MHz-Using the Verilog HDL language implementation of a DDS, can occur 0-10Mhz sine, square, triangle wave, frequency step tunable, FM modulation, AM modulation, adjusta
2psk
- 2psk 模块的Verilog实现 （载波为方波）-2psk Verilog module implementation (carrier for the square wave)
Verilog-hdlFPGA
- 关于FPGA的提高篇，Verilog HDL语言写的， 包含LCD控制VHDL程序与仿真，AD/DA，MASK，FSK，PSK，正弦波发生器，等等经典程序-Articles on improving the FPGA, Verilog HDL language, and includes LCD control procedures and VHDL simulation, AD/DA, MASK, FSK, PSK, sine wave generator, and so the classi
MATLAB-and-verilog
- 1 采用正弦波，方波进行同步调制，实现调制信号、已调信号、解调信号的波形、频谱以及解调器输入输出信噪比的关系。 2 采用Verilog语言编写有符号的五位乘法器 3 实现数字与模拟调制-A sine wave, square wave synchronous modulation to achieve the modulation signal, the modulated signal, the demodulated signal waveform, spectrum and sig
ahdl--sine-wave-code-with-rom-look-up-table_imp.r
- hi this an verilog codes-hi this is an verilog codes
三角函数的Verilog HDL语言实现
- 以Actel FPGA作为控制核心，通过自然采样法比较1个三角载波和3个相位差为1 200的正弦波，利用Verilog HDL语言实现死区时间可调的SPWM全数字算法，并在Fushion StartKit开发板上实现SPWM全数字算法。(With Actel FPGA as the control core, between 1 and 3 triangular carrier phase difference of 1200 sine wave by natural sampling, rea