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create_COE_file_from_vector
- Create COE for Xilinx FPGA
Simplex
- coe of simplex by java langage
ltfat-1.4.5-win64
- 线性时频分析工具 线性时间频率分析工具箱是一个Matlab /八度 工具箱进行时频分析。它的目的是作为一个 教育和计算工具。工具箱提供了3 dierent时频转换,2个运营商建设 随着构建windows(lter原型)和例程 为操纵coecients例程。为了方便学习 工具箱,工具箱提供的例子。-The Linear Time-Frequency Analysis Toolbox The Linear Time Frequency Analysis Toolbox
Spwm code
- Sine pwm coe generation using microcontroller
bmp2bin
- 将BMP图像信息转换成coe文件,用与Xilinx fpga的ROM初始化-turn the information of BMP to coe document for Xilinx FPGA
Lab_2
- lab2 code for lab 2 coe
jpeg-image-to-.coe-file-in-matlab
- fmnbcv,mbnc,mvnbc, ncbvdkjbhcmfnbcm n bvxjcfbvcf cvjxndbvnc mnvbcvmbncv,m, nvcndxbvxn v cncmvnc,mbn nvxkjnbcvmbn nvcbncv,mbn cv,m v cxmvn -fmnbcv,mbnc,mvnbc, ncbvdkjbhcmfnbcm n bvxjcfbvcf cvjxndbvnc mnvbcvmbncv,m, nvcndxbvxn v cncmvnc,mbn nvxkjnbcvm
makecoe
- fpga coe 文件生成工具，可以生成1byte，2byte，4byte类型的coe文件，可以通过bin文件、hex文件以及obj文件产生coe文件-fpga make coe file tool,can build 1byte，2byte，4byte type coe file,can bin,hex or obj file produce
COE
- 神经网络估计船舶动态项，实现船舶曲线跟踪-nn network estimate daming term，vessel path following
lyapunove-coe
- 计算hopf分叉的maple程序,可得分岔的稳定性及判断分岔方向-hopf bifurcation procedure
cPP-classical-code
- C++ 短小精悍的源代码汇总，包含多种应用的代码，可借鉴使用-C++ source code collections，include many kind of source coe
Dec2bin
- 十进制数转换成二进制补码，并将结果写入txt。低通滤波器设计、多相滤波器组设计，并将系数写入txt或者coe文件，可用于FPGA设计-Decimal numbers into binary complement, and writes the result txt. Low-pass filter design, polyphase filter bank design, and coefficient writing or coe txt file that can be used for F
nlms
- This is an nlms algorithms for wavelet coe-This is an nlms algorithms for wavelet coeff
8-TFT_24
- 基于Xilinx Spartan6自制开发板实验，2.4存TFT屏静态刷新特定图片。如果要修改图片，请使用Matlab将图片生成*.coe格式，生成ROM加载。-Development board based on Xilinx Spartan6 homemade experiment, 2.4 TFT screen kept static refresh specific picture. If you want to modify the picture, the image is gene
IP_COE_Abs2Rel
- 编程辅助软件，将Xilinx ISE 14.x IP核含有的COE文件从绝对路径改成相对路径-Progrmming assisting software, Xilinx ISE 14.x IP core have COE file absolute path change into relative path
vga2
- 本功能主要实现了VGA的显示，分辨率为1024*768，包内有制作好的coe文件存入rom，适合xilinx芯片-This function is mainly to achieve a VGA display with a resolution of 1024* 768, the bag has produced a good coe file into the rom, for xilinx chip
write
- 使用golang生成一个coe文件，初始化rom。其中随机产生10000个数值作为初始化值-Use golang generate a coe file to initialize rom. Wherein the randomly generated value as the initial value 10000
sin_rom
- 在rom文件中生成正弦波COE文件，在Matlab中生成正余弦波形的浮点值，并量化为16bit定点波形数值- Generate sine wave COE file in rom file
SOES-master
- Simple Open Source EtherCAT Slave ==== SOES (Simple OpenSource EtherCAT Slave Stack) is an opensource slave stack that is very easy to use and provides a small footprint. It is a good alternative to more complex stacks on the market.
HT66F50-io-test
- HT66F50 IO test sample coe -HT66F50 IO test sample coe