搜索资源列表
JTAG_XILINX_ARM_LPT_PROGRAMMER
- This is LPT JTAG programmer for Xilinx FPGA/CPLD chips and for ARM-core microcontrollers.
CPLD-radom
- 基于C P L D 的伪随机序列发生器,用FPGA产生随机序列的-CPLD-based pseudo-random sequence generator, generate random sequences using FPGA
jtagdownload
- alter cpld下载线制作方法集合,自己做就行,不用花40元去买了-alter cpld download cable production method of collection, make their own on the line, do not have to spend 40 yuan to buy a
CC1100_CPLD
- 基于CC1100和CPLD的时差法测距实验 以GPS秒脉冲为复位信号及开始计时的时间基准, 同时作为无线发射的触发信号。 计时由CPLD计数时钟脉冲实现, 当发射机发射完毕后CC1100模块给出中断,中止主机CPLD的计时, 得到发射时间脉冲数n1; 当接收机CC1100接收到数据包后,给出中断, 提醒单片机处理,并且中止接收部分CPLD的计时, 得到收到时间脉冲数n2。 由n2-n1乘以时钟周期可得电波的传播时间。 程序包括:CPLD计时器程
rs232
- 这是cpld,EPM240数据通信rs232程序,希望与大家分享-This is cpld, EPM240 data communication rs232 procedure, hoping to share with you
an428
- MAX II CPLD 设计手册 英文版-MAX II CPLD Design Guidelines
ATmega128
- 简要介绍: 主要芯片: CPU:ATmega128L SRAM:SR61L256BS-8 CPLD:XILINX XC95144XL SFLASH:AT45DB081B ETHERNET:CS8900A USB:PDIUSBD12 LCD:122x32 LMC62_095_M POWER:LM2596S-3.3 RS232:MAX3232 软件:RS232,SRAM,CPLD调试通过,uCosII可以运行,ethern
CPLD-FPGA
- FPGA的学习指南,绝对经典,内容比较超值,我已经细心读过了,讲解清晰,快速入门。-FPGA-study guide, an absolute classic, the content of more value, I have carefully read, and to explain clearly, Getting Started.
SimpleDriver
- Wince5.0+S3C2440扩展总线挂接CPLD的驱动-Wince5.0+ S3C2440 expansion bus drivers hooking CPLD
01171699
- 51单片机+CPLD结构,小板上集成了发光二极管,蜂鸣器,数码管,红外接收头,继电器,实时时钟,按键,AD(TLC1549),DA(TLC5615),232串口,LCD1602接口,LCD12864接口,单片机和CPLD引脚扩展接口,集成5V稳压电源,USB电源接口等功能。 -hhhhhhhhhhhhhhhhhhhhhhhhhhhhh
Lcd_Driver
- TFT LCD驱动,CPLD,XL95144-verilog-TFT LCD DRIVER-verilog
CPLD
- 基于CPLD 的交通灯设计
vhdl_sram_ctrl
- Sycronous SRAM in CPLD or FPGA module... tested by Altera MaxPlusII or Quatus -Sycronous SRAM in CPLD or FPGA module... tested by Altera MaxPlusII or Quatus II
DEC6713
- DSP 6713型号的基本源程序 可以对67系列进行初始化,对EDMA,CPLD进行配置。-6713 DSP basic models of 67 series source program can be initialized, to EDMA, CPLD configuration.
VHDL_Data
- 潘松的VHDL使用教程,已经制作书签,阅读方便,是学习VHDL新手的必备资料,FPGA/CPLD开发者可以参考的资料,-Pinson use of VHDL tutorial have produced bookmarks, reading easy to learn the essential information on VHDL novice, FPGA/CPLD developers can refer to the information,
cpldtest
- 一个cpld的点灯测试程序,用verilog hdl语言编写,具有参考性-A cpld the lighting test program, using verilog hdl language, with reference to sexual
CPLD(ZFZ2009-2-24)
- 转速表CPLD源程序代码,具有频率检测,数码管显示刷新,反转检测功能-Tachometer CPLD source code, with a frequency detection, digital tube display refresh, reversal detection
eda
- cpld开发板电路图,刚下载的,还不错,给大家看看。-the map of cpld developed board。
Motor_drive_board
- 电机驱动板,采用ipm,cpld保护,电流电压检测,编码器信号处理-Motor drive board, using ipm, cpld protection, current and voltage detection, signal processing encoder
quaddecoder_verilog_ise11.2_used_09042010
- Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File. The Pinout is descr ipted in the Constrained file quad.ucf. To use them, y