Xilinx MATLAB、SysGen的 图像 DCT工程-Xilinx MATLAB, SysGen image DCT works

用FPGA实现的JPEG压缩器，可以直接使用，内含完整文档说明-This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second at the maximum resolution 352x288 (on XC2V

研究生课程 ： 来源于Xilinx公司，二维DCT变换代码。-Graduate courses: from Xilinx, 2D DCT function implementation verilog code.