搜索资源列表
divider
- 高效率的VERIFLOG描述语言的除法器,比一般的速度高-Efficient VERIFLOG descr iption language of the divider, than the average high speed
9600divider
- 任意分频器,可以实现FPGA的CLK分频功能，已通过编译-Arbitrary frequency divider can be achieved FPGA-CLK sub-band capabilities, has passed the compilation
divider
- 带时钟及控制的多位除法器设计，利用状态机来实现控制-multi-cycle divider design
clk_divider
- Simple Clk Divider for FPGA design in Verilog -Simple Clk Divider for FPGA design in Verilog
clock_divider
- clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc-clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc
divider
- 介绍了verilog设计中一种分频器的写法，很通用实惠，方便移植-Introduced the verilog design the wording of a kind of divider, a very common benefit, to facilitate migration
div_n
- verilog占空比50奇偶任意 奇偶任意分频器！包括测试代码-verilog random duty cycle of 50 odd parity arbitrary divider! Including test code
divider
- 用VERILOG实现一个被除数为8位、除数为4位的高效除法器-With VERILOG implement a dividend for the 8-bit, 4-bit effective divisor divider
A-Universal-Programmable-Dual-Divider
- 一种通用的可编程双模分频器A Universal Programmable Dual Divider-A Universal Programmable Dual Divider
time-divider
- 时钟分频器，这个虽然简单一点，但还是觉得很不错的，-Clock divider, this is simple point, but still felt very good,
diwu
- 应用VHDL语言编写设计一个正负脉宽可控的4分频的分频器。程序简单易懂；-Application of VHDL language to design a controlled positive and negative pulse frequency divider 4. Procedures are simple and easy to understand
Sequential-Divider
- Partial design of a sequential divider using GATES
Fixpoint-Divider
- 定点除法器的设计,关于定点除法器的原理，和设计，以及电路设计-Fixpoint Divider Design
divider
- FPGA除法器的使用32位的，有商和余数-FPGA using 32-bit divider, there are the quotient and remainder
divider
- 16位定点无符号数除法器，除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成-Unsigned 16-bit fixed-point divider, divisor, dividend by 16-bit integer and 16 fractional bits, commercial 32-bit integer and 16 by the decimal form, the remainder from 32 fractional bits
frequency-divider
- anything frequency divider-frequency divider
VHDL-test-code-divider
- VHDL实验代码：除法器，是一个基于VHDL语言开发的小程序，是关于除法的算法，比较实用-VHDL test code: divider, is a VHDL-based language developed by a small program, on the division algorithm, more practical
clock-divider
- VHDL code for clock divider circuit. There are two modules: one output divide by 4 and other outputs divide by 6
File-Divider-vb
- 文件分割机，是一个很好的工具，是学习的好源码。-File Divider is a good tool, is a good source for learning.