搜索资源列表
clkt2xxx_dpll
- OMAP2-specific DPLL control functions driver
dpll44xx
- OMAP4-specific DPLL control functions driver for Linux.
dpll3xxx
- OMAP3/4 - specific DPLL control functions
clkt2xxx_dpllcore
- DPLL + CORE_CLK composite clock functions
verilog-pll
- 用verilog写的倍频电路 文件中介绍DP-The multiplier circuit file by verilog introduced DPLL
dpll2
- 数字锁相环的vdhl实现，鉴相器，计数器，压控振荡器，和分频器-Vdhl DPLL implementation, the phase detector, a counter, a voltage controlled oscillator, and a frequency divider
ADPLL-patent
- 全数字锁相环的几个专利，全部为英文，很好的参考资料-DPLL patent
00258213
- This paper presents a generalized nonlinear (Markov) analysis technique for evaluation of the statistical performance of uniformly sampled digital phase-locked loops (DPLL). Recently proposed synchronization algorithms use more discrete t
dpll
- 用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证-verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider
dpll44xx
- OMAP4-specific DPLL control functions for Linux v2.13.6.
clkt2xxx_dpll
- OMAP2-specific DPLL control functions.
clkt_dpll
- OMAP2 3 4 DPLL clock functions.
clkt2xxx_dpll
- enable DPLL autoidle bits.
power-management
- Lock USB DPLL on OMAP4 devices so that the L3INIT power domain can transition to retention state when not in use.
code
- 本源码是基于VHDL语言环境下的基础实验源码，共分七个部分。分别是：序列检测器、数字密码锁、四位有符号数除法、同步FIFO、DPLL的设计以及Cordic 算法实现。对于VHDL的初学者具有极大的参考价值。-The source is based on experimental basis source VHDL language environment, it is divided into seven sections. They are: the sequence detector, di
io_ordering
- DPLL rate rounding: minimum DPLL multiplier, divider values.
fsys
- Finalizes DPLL registration process. In case a failure (clk-ref or clk-bypass is missing), the clock is added to retry list and the initialization is retried on later stage.
ti
- CM_CLKEN_PLL.EN bit values - not all are available for every DPLL.
scc
- experimental fullduplex mode with DPLL BRG for MODEMs without clock recovery. -experimental fullduplex mode with DPLL BRG for MODEMs without clock recovery.
DPLL
- 一个全数字锁相环，可用于信号的复用中，进行调制和借条操作。-A digital phase-locked loop can be used to signal multiplexing, modulation and IOU operations.