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fpga与PC机的串口通信
- 基于VerilogHDL 的FPGA与PC的串口通信代码,已经测试过,绝对可以用
RS232串口通信协议
- RS232串口通信协议,verilog实现,通过FPGA完全调通。,RS232 serial communication protocol, verilog achieved entirely through the FPGA transfer pass.
FPGA-URAT.rar
- FPGA与PC串口自动收发程序,verilog源程序,FPGA and the PC serial port automatically sending and receiving process, verilog source code
rs232
- 完整的RS232 Verilog源代码,支持波特率可调,支持调试命令,配合串口调试工具,可作为FPGA开发中的调试平台。-Full RS232 Verilog source code, support for baud rate is adjustable to support debugging command, with the serial debugging tools can be used as the debugging FPGA development platform.
uart
- 串口通讯 PC发送FPGA接受后回传 verilog语言-uart verilog
UART
- 本人自己编写的FPGA异步串口通信模块(UART),基于QuartusII环境,verilog语言编写,包含仿真和全部程序及说明,验证通过,具有很好的稳定性和参考价值!-I have written of the FPGA asynchronous serial communication module (UART), based on QuartusII the environment, verilog language, including simulation and all the pr
FPGA-RS232-verilog
- fpga上的串口驱动程序,包括接收主机来的数据(deserial)和发送由FPGA产生的数据(serial).该程序的调试需要借助串口调试助手-serial port driver on the fpga, including the receiving host to the data (deserial) and send the data generated by the FPGA (serial) to pc. The program needs the serial debug deb
Serial
- FPGA与PC串口通信的Verilog HDL 程序-FPGA and the PC serial communication procedures Verilog HDL
sim_uart
- uart 收发器 verilog 代码,实现自收发功能 sys clk = 25m, baud 9600 停止位1, 无校验位; 代码实现了串口自收发功能,及把从 PC 收到的内容都发送会 PC, 其他波特率,自行修改代码即可,在 alter 的FPGA 上调试通过; -verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no par
FPGUART
- verilog语言,FPGA,串口。 波特率9600,数据位8位,停止位1.-verilog language, FPGA, serial. 9600 baud, 8 data bits, 1 stop bit.
IIC读写EEPROM发送到PC串口
- 能实现用IIC读EEPROM并且将读取的数据通过串口发送到PC端,以及在PC端通过串口发送数据给FPGA,再利用IIC将数据写入EEPROM(The program can realize that FPGA read the data from EEPROM by IIC and then send it to PC by UART,and that PC send the data to FPGA by UART and then write the data to EEPROM by
基于FPGA的串口通信系统
- 该设计是基于 FPGA 的串口通信系统模拟仿真,通过对 RS-232 串行总线 接口的设计,掌握发送与接收电路的基本思路,并进行串口通信。采用 Verilog HDL 语言对 UART 波特率产生模块、数据发送模块、接收模块进行硬件描述, 再将其整合为一个 RS-232 收发模块,最终在顶层模块中将两个 RS-232 模块例 化,实现两块 FPGA 芯片全双工通信的设计。(Design of serial communication system based on FPGA)
FPGA实现串口解析
- 用verilog语言不同的编写方式来 实现各种复杂串口通讯(use the verilog to uart)
07_uart_test
- fpga 串口 Verilog 黑金的板子,入门(fpga uart test xilinx)
串口通讯
- EP208Q8F17C8芯片的串口通讯程序(uart communication verilog code)
verilog串口通信程序
- 串口通信程序,用于fpga的串口收发,并讲解了串口通信原理。(Serial communication program is used to receive and transmit the serial port of FPGA, and the principle of serial communication is explained.)
No.201710061347=UART_Verilog
- 1.硬件平台: FPGA; 2.编程语言: Verilog; 3.串口通信RS232的Verilog实现版本;(1. hardware platform: FPGA; 2. programming language: Verilog; The Verilog implementation version of 3. serial port communication RS232;)
tx_interface_project
- 带FIFO的串口发送模块,简单的FPGA串口发送模块(Serial transmission module with FIFO)
基于FPGA与PC串口自收发通信-Verilog
- 基于FPGA与PC串口自收发通信-Verilog(Self-transceiving Communication Based on FPGA and PC Serial Port-Verilog)