搜索资源列表
7tgq
- txt文本格式处理器，可以分割txt格式，txt格式与html的相互转换-txt text processor, can be divided txt format, txt and html format of the mutual conversion
Performance_and_Programmability_of_the_Cell_Proces
- Performance and Programmability of the Cell Processor，Cell处理器的性能和可编程性分析，Cell作为成功的多核处理器将在高性能计算领域产生深远影响-Performance and Programmability of the Cell Processor, Cell processor performance and analysis of programmable, Cell as a successful high-performanc
RISC
- source and benchmark test for the registery parts of a RISC processor-source and benchmark test for the registery parts of a RISC processor
graphics_pipeline
- Implementation of GPU (Graphics Processing Unit) that rendered triangle based models. Our goal was to generate complex models with a movable camera. We wanted to be able to render complex images that consisted of hundreds to thousands of triangles. W
IniProcessor
- 用Java实现的INI文件处理的类， 弥补Java API中缺少INI文件处理的缺陷-an Ini file processor implemented by java
DualDSPbasedembeddedvisualfeedbackcontrolsystemfor
- 为了满足多种电力电子变换器对其控制平台的不同要求,缩短开发时间,实现控制平台硬件的通用化和软件 的模块化,在基于双定点数字信号处理器(DSP)TMS320LF2407的大容量变换器专用控制平台的基础上, 提出了电力电子变换通用控制平台的设计目标。描述了基于定点和浮点DSP(TMS320F2812和TMS320VC33)的通用 控制平台各单元的设计方法。介绍了基于MATLAB实时工具箱(RTW)的调试方法。实验结果验证了设计和调试方法 的正确性和可行性,该通用控制平台达到了设计目标
Multi_Cycle_Microprocessor_with_Control
- Multi Cycle processor with control logic Verilog Computer organization and design
mips_multi
- mips processor multicycle non-pipelined microprocessor by verilog
87361039
- 于一个8位处理器的分析，和源代码，VHDL语言设计，经过测试-An 8-bit processor in the analysis, and source code, VHDL language design and tested
sc_mips_core.tar
- A SystemC MIPS processor model.
webCam-FPGA
- 使用Verilog控制美光CMOS图像处理器，并转存到SDRAM中。使用FPGA为QL的带fuse系列-Control the use of Verilog Micron CMOS image processor and SDRAM in转存到. FPGA for use with QL series fuse
GraduationProject
- 进行了一个8位CISC处理器的设计与实现，该微处理器含有计算机基本的功能模块，并对存储器进行了层次化设计。指令系统中的指令分为四大类共十六条，其中包括算术逻辑指令、I/O指令、访存、转移指令和停机指令。在处理器的实现过程中,首先给出了数据通路结构,然后采用VerilogHDL进行硬件电路描述,并对每一个模块进行功能仿真以验证设计的正确性。最后对整个处理器执行程序进行指令验证,并得到综合后的网表。-Conducted an 8-bit CISC processor design and imple
ADS1.2Chinese_Tor
- 32位 ARM嵌入式处理器的调试技术。叙述了有关于JTAG的技术-32-bit ARM embedded processor debug technology. Described on JTAG technology
mmarm_EDACN
- 用FPGA实现ARM嵌入式处理器功能的Verilog源码及说明-FPGA with embedded ARM processor to achieve the functional descr iption of Verilog source code and
CPU_Architecture
- Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks. External hardware accelerator is used for network packet processing. The common netw
spru671
- OMAP5910 Dual-Core Processor MPU Subsystems Reference Guide
KM
- vhdl code 16 bit processor
multiprocessor
- multi processor scheduling with genetic algorithm
mips
- 使用verilog設計的MIPS處理器，mips處理機的模擬且可合成驗証-MIPS processor using the verilog design, mips processor synthesis of analog and can be verified
nnARM_tb01_09_02
- arm processor verilog code