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pwm_source
- ALTERA PWM電路 這是一個ALTERA的PWM電路，可以整合到NIOSII IDE中，來完成一個PWM的系統。-Altera PWM circuit Altera This is a PWM circuit, NIOSII can be integrated into the IDE, to complete a PWM system.
altera_avalon_pwm
- Avalon altera pwm generator. Directly use in SOPC.
SoftwareExample
- altera de1开发板 dma,pwm...实验源码
PWM_LED.rar
- 基于ALTERA公司NIOSII的LED灯控PWM IP核设计,ALTERA-based company controlled NIOSII the LED lamp PWM IP-core design
pwm_avalon_interface
- altera 公司内部PWM的HDL及驱动代码-altera internal PWM and driver of the HDL code
pwm_source
- Altera官网上关于SOPC中自定义组件（PWM）的实例，官网上现在没了。。可很多书上都在用-Altera in the official line on the SOPC custom component (PWM) of the examples are not the official line. . Can be a lot of books are in use. . .
PWMAvalonExample
- PWM generation,Altera standard function.
avalon_pwm
- altera公司的PWM设计，非常详细！-altera' s PWM design, very detailed!
Altera_FPGA_pwm
- 基于FPGA（ALTERA公司的FPGA）PWM的测试程序。-Based on FPGA (ALTERA' s FPGA) PWM test procedures.
Altera_FPGA_motor
- 基于Altera的FPGA的开发板的PWM测试程序。板子是周立功的MagicSOPC的。-Altera' s FPGA-based development board of the PWM test procedure. Ligong week the board is the MagicSOPC.
PWM_VerilogHDL
- altera公司网站上的详细的PWM设计的Verilog hdl源程序，大多数都采用这个-altera company' s Web site the detailed design of the PWM source Verilog hdl, most have adopted this
ADC0809
- 完整ADC0809的时序，采用VHDL语言编写，在Altera cycloneI/II系列下的EP1C6\EP2C5\8平台下测试完成，稳定-ADC0809 Driver by VHDL
PWM_GEN
- 这是Altera PWM生成的一个实例。包含project文件，源代码，仿真文件。经过验证，实际可用。-This is an example of Altera PWM generated. Contains the project files, source code, simulation files. After verification, the actual available.
meanFilter
- This is a variable length window averaging filter that uses an MCP3002 ADC with SPI interface to sample an analog input, and has a PWM that can be run through a low-pass filter to produce an analog output. The design was simulated in Modelsim with no
MyPWM
- 基于FPGA ALTERA EP2C5Q8208C8，自制PWM控制器，配合上位机定时器-based on FPGA ALTERA EP2C5Q，PWM controller,with MCU TIMER
Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Ex
- 来自于ALTERA官方网站。 本文档详细介绍怎样利用MAX® II CPLD 来实现脉冲宽度调制(PWM)。本设计还利用了MAX II CPLD 的内部用户闪存振荡器，不需要采用专门的外部时钟。 附有verilog源程序。-From ALTERA website. This document details how to use the MAX ® II CPLD to implement pulse width modulation (PWM). This design
PWM-waveform
- 用Altera Quartus II 的VHDL语言完成的PWM波形产生的源代码-Altera Quartus II VHDL with the completion of the PWM waveform generation language source code
DE0_NANO_default
- PWM波控制LED亮度,使用Verilog语言，开发环境为Altera的quatus 11，使用的的DE0-Nano-PWM wave control LED brightness, the use of the Verilog language development environment for Altera' s quatus 11, use the DE0-Nano
pwm
- 使用Altera公司的FPGA的软化，利用NIOS完成PWM功能-Using Altera' s FPGA softening, use NIOS complete PWM function
pwn-FOR-60-HZ
- THis code is for Spwm based inverter.with 25khz carrier frequency of pwm and 60 hz frequency which is modulated on pwm.compiled in altera Quartus