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Quartus7.2
- 通过VHDL实现4位全加器,8位全加器,和8位通用寄存器的设计-4-bit full adder 8-bit full adder 8-bit register using vhdl
RS232_FIR
- Quartus II was a development tool of CPLD / FPGA by Altera Company. Quartus II provides a fully integrated circuit structure and has nothing with the development package environment, it has all the features of digital logic design, it is including: a
cpu
- 一个简单的CPU设计,支持add,sub,mvi,mv四条指令,用Verilog语言编写,在Quratus II上编译通过,仿真正确。-A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.
Example-b8-2
- 使用ModelSim对Altera设计进行时序仿真的简要操作步骤 1.建立工程,设置仿真工具选项参数 2.使用Quartus II编译工程 3.建立仿真工程 4.Altera仿真库的编译与映射 5.编译HDL源代码和Testbench 6.启动仿真器并加载设计顶层 7.打开观测窗口,添加信号 8.执行仿真-Using ModelSim Altera design for timing simulation of brief steps 1. Establish pro