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iic总线控制器VHDL实现
-- VHDL Source Files:
i2c.vhd -- top level file
i2c_control.vhd -- control function for the I2C master/slave
shift.vhd -- shift register
uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC
u
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verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) mo
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MANIK is a 32 bit RISC Microprocessor. The salient features of the processor are listed
below.
Features
Hardware Features
• Data Path Width 32 bits, with Four stage pipeline.
• Mixed 16/32 bit instructions for code density
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register file in vhdl and alu
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用VHDL代码写的模拟微处理器核程序，有计算模块和register file 等模块，并包含测试程序，调试程序 ACTIVE HDL-Simulation with the VHDL code is written in the microprocessor core procedures, such as computing modules, and register file module, and includes test program, the debugger ACTIVE HDL
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编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现，包含整个QuartusＩＩ的工程文件，解码方式为寄存器交换法-Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange
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文件包含了寄存器，移位寄存器，可能计数器，计数器等用VHDL实现的功能模块。-File contains the register, shift register, may counter, counter, implemented with the VHDL modules.
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register file using verilog
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Xilinx提供的I2C控制器代码,Master/Slave全功能-
Readme File for I2C Customer Pack
Created: 7/8/99 ALS
Revised: 11/4/99 ALS
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ov7670的寄存器赋初值文件，用verilogHDL编写，设定为rgb格式，640*480大小。-ov7670 register initial value file, with verilogHDL write, set to rgb format, 640* 480 size.
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antidad_a EQU s0
talto EQU s1 Rename register sX with <name>
tbajo EQU s2
indicador EQU s3
cantidad_b EQU S4 Define constant <name>, assign value
name ROM output file generated by pBlazIDE assembler
VHDL "ROM_form.vhd", "ser
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This file is an asynchronous vhdl Register. It registers the input vector into the output vector when the Enable variable is high.
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