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descript
- 时序电路描述-Descr iption of sequential circuits
simple_verilog
- cycloneII Quartus verilog开发的简单时序电路-cycloneII Quartus verilog to develop a simple sequential circuit
Sequentialdivider
- program to perform sequential divider in vhdl
novogsp
- Algorithm GSP in C for patterns sequential
shifter
- 移位运算器SHIFTER 使用Verilog HDL 语言编写,其输入输出端分别与键盘/显示器LED 连接。移位运算器是时序电路,在J钟信号到来时状态产生变化, CLK 为其时钟脉冲。由S0、S1 、M 控制移位运算的功能状态,具有数据装入、数据保持、循环右移、带进位循环右移,循环左移、带进位循环左移等功能。 CLK 是时钟脉冲输入,通过键5 产生高低电平M 控制工作模式, M=l 时带进位循环移位,由键8 控制CO 为允许带进位移位输入,由键7 控制:S 控制移位模式0-3 ,由键6 控制
DigitalCircuitExerciseAnswer
- 电子技术基础(第五版数字部分)康华光 课后习题解答 1 数字逻辑概论 2 逻辑代数与硬件语言描述 3 逻辑门电路 4 组合逻辑电路 5 锁存器和触发器 6 时序逻辑电路 7 存储器 8 脉冲波形的变换与产生 9 数模与模数转换器-The basis of electronic technology (the fifth edition of the digital part), Culture and Sport Exercise Huaguang ans
Verilog_example_guide
- 详尽介绍了VERILOG编程过程中的组合逻辑和时序逻辑设计方法,同时对仿真程序的编程和使用也做了完美的讲解,便于快速学习掌握-Detailed descr iptions of the course of the VERILOG a combination of programming logic and sequential logic design, simulation program at the same time the use of programming and have als
0514003
- 根据汽车内饰等行业需求,对皮制品加工的优化排样问题进行了研究.创新地采用离散化处理方式,同时引进边界约束,使排样过程与皮料和样片的几何信息无关,使用基于顺序的启发式底左布局将样片顺次布置到皮料上-According to the demand for such industries as automotive interior trim, leather processing for optimal layout problem is studied. Innovative approach o
QuadD
- 四路D型触发器 这个例子表明一个条件任务状态能够怎样被使用来描述连续的逻辑-Quad D-Type Flip-flop This example shows how a conditional signal assignment statement could be used to describe sequential logic
EMarket
- This example for E-Market to use sequential file instead of database.-This is example for E-Market to use sequential file instead of database.
divide
- It is n-bit sequential divider in verilog language
Flashcontrollerxilinx
- Single power supply operation — Full voltage range: 2.7 to 3.6 volt read, erase, and program operations — Separate VCCQ for 5 volt I/O tolerance n Automated Program and Erase — Page program: 512 + 16 bytes — Block erase: 8 K + 256 bytes
CRF
- 条件随机场用于NLP中命名实体,组块分析。-CRF++ is a simple, customizable, and implementation of Conditional Random Fields (CRFs) for segmenting/labeling sequential data. CRF++ is designed for generic purpose and will be applied to a variety of NLP tasks, such as Named
Minaret.tar
- Minaret: retiming edge-triggered circuit for improved performance and higher clock frequency by moving combinational logic gates across sequential elements
tixingtu
- 经验设计法简介 梯形图程序设计是可编程控制器应用中最关键的问题 ,PLC 梯形图程序设计常用方法有 : 经验设计法、顺序控制设计法和逻辑代数设计法等。 PLC 梯形图程序用“经验设计法”编写 , 是沿用了设计继电器电路图的方法来设计梯形图 , 即在某些典型电路的基础上 , 根据被控对象对控制系统的具体要求 , 不断地修改和完善梯形图。有时需要多次反复地进行调试和修改梯形图 , 不断地增加中间编程元件和辅助触点 , 最后才能得到一个较为满意的结果。因此 , 所谓的经验设计法是指利用已经的经验
TMNOSNGS3
- GPS network adjustment using sequential method
watercontrol
- 可通航水库闸门简易控制系统概述:水库闸门具有如下四重功能,控制蓄水、及时泄洪、控制通航、保证发电。故一个功能完善的水库系统应有实现发电控制(发电闸门,设为一组)、泄洪或供水需要(泄洪供水闸门,设为一组)及维护通航(通航闸门,上下游各一组)等三种功能的闸门系统。本课题拟设计一水库闸门控制系统,通过组合电路与时序电路共同实现一闸门开关控制器,在试验阶段用LED指示灯亮灭来模拟闸门开关-Navigable dam gate control system outlined in the Summary:
as
- 本程序首先对数组a中的10个数从大到小排序并输出排序结果。然后输入要插入的整数n。再用一个for语句把n和数组元素逐个比较,如果发现有n>a[i]时,则由一个内循环把i以下各元素值顺次后移一个单元。后移应从后向前进行(从a[9]开始到a[i]为止)。后移结束跳出外循环。插入点为i,把n赋予a[i]即可。 如所有的元素均大于被插入数,则并未进行过后移工作。此时i=10,结果是把n赋于a[10]。最后一个循环输出插入数后的数组各元素值。 -This procedure first arra
SGeMS-2.0
- For Windows systems, only Visual C++ 6 质统计分析软件代码-The Stanford Geostatistical Modeling Software (SGeMS) SGeMS is a software for 3D geostatistical modeling. It implements many of the classical geostatistics algorithms, as well as new d
Talg_det
- The real-valued version of this priority first stack-based sequential decoding algorithm is based on a decoding tree of m+1 levels where each node has 2*xMax children-The real-valued version of this priority first stack-based sequential dec