搜索资源列表
fpga2dsp
- Altera Stratix II FPGA与TS201 DSP通过链路口通信的程序-Altera Stratix II FPGA and TS201 DSP through a chain junction communication procedures
bus1
- DSP TS201总线通信程序，与Altera Stratix II FPGA-DSP TS201 bus communication procedures, and the Altera Stratix II FPGA
aib-01017-soc-fpga-overview
- Altera SOC platform overview for Stratix-V, ArriaV FPGA families, with ARM Cortex A9 Dual COre Hard Macro embedded. This is a seminar document, attended in May 2013
SOFTWARE
- Streaming data over Ethernet.Using for interface with Ethernet MAC on Stratix IV Board
StratixII
- 基于stratix的千兆接收器通道的字对齐技术-stratix ALLIGE
i2cBUS
- Altera的I2C总线FPGA程序，内有详细使用说明- The I2C Controller is available in VHDL and is optimized for the Altera® APEX™ , Stratix® , and Cyclone™ device families. All of the register addresses are defined as constants in the VHDL source
hip_s4gx530_gen2_x8_128
- 声明：这段程序来自别人，知识产权他人。 对于学习Stratix IV GX530这套开发板有一定帮助。(This a test program from other people. It is helpful for others to learn the Stratix IV GX FPGA Development Kit Board.)
ACCx42_AvalonST_Input
- This module does pipelined accumulate operation with 42 bit int value, usually used in dsp, Proved in Altera Stratix FPGA devices
Quadrature_MACx42_AvalonSt_Input v1.0
- This module does Complex MAC based on Altera Stratix 2 DSP Blocks.
rtl
- 基于S10新品的2x2矩阵乘模块，附带双精度的乘法，除法ip核(2x2 matrix multiplication module based on S10 new product, with double precision multiplication, division IP kernel)
NIOS-II常用函数详解
- Nios II系列软核处理器是Altera的第二代FPGA嵌入式处理器，其性能超过200DMIPS，。Altera的Stratix 、Stratix GX、 Stratix II和 Cyclone系列FPGA全面支持Nios II处理器，以后推出的FPGA器件也将支持Nios II。(The Nios II family of soft core processors is the second generation of Altera's FPGA embedded processor tha