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文件名称:rtl

  • 所属分类：
    VHDL/FPGA/Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2018-01-24
  • 文件大小：
    577kb
  • 已下载：
    0次
  • 提 供 者：
    Rd***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

基于S10新品的2x2矩阵乘模块，附带双精度的乘法，除法ip核(2x2 matrix multiplication module based on S10 new product, with double precision multiplication, division IP kernel)
相关搜索： verilog hdl STRATIX

(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
rtl\00_ip_core\Float_Add\.qsys_edit\filters.xml 66 2018-01-18
rtl\00_ip_core\Float_Add\.qsys_edit\Float_Add.xml 92709 2018-01-18
rtl\00_ip_core\Float_Add\.qsys_edit\preferences.xml 290 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\altera_fp_functions_171\sim\dspba_library.vhd 13298 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\altera_fp_functions_171\sim\dspba_library_package.vhd 2713 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\altera_fp_functions_171\sim\Float_Add_altera_fp_functions_171_herhlui.vhd 185563 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\altera_fp_functions_171\synth\dspba_library.vhd 13298 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\altera_fp_functions_171\synth\dspba_library_package.vhd 2713 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\altera_fp_functions_171\synth\Float_Add_altera_fp_functions_171_herhlui.vhd 185563 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\Float_Add.bsf 3910 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\Float_Add.cmp 429 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\Float_Add.csv 791 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\Float_Add.html 7972 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\Float_Add.ppf 507 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\Float_Add.qgsimc 7535 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\Float_Add.qgsynthc 7535 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\Float_Add.qip 16251 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\Float_Add.sopcinfo 23370 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\Float_Add.spd 642 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\Float_Add.xml 9538 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\Float_Add_bb.v 248 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\Float_Add_generation.rpt 6418 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\Float_Add_inst.v 374 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\Float_Add_inst.vhd 712 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\sim\aldec\rivierapro_setup.tcl 18012 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\sim\Float_Add.v 677 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\sim\mentor\msim_setup.tcl 18689 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add\synth\Float_Add.v 677 2018-01-18
rtl\00_ip_core\Float_Add\Float_Add.ip 29867 2018-01-18
rtl\00_ip_core\Float_Div\.qsys_edit\filters.xml 66 2018-01-23
rtl\00_ip_core\Float_Div\.qsys_edit\Float_Div.xml 92709 2018-01-23
rtl\00_ip_core\Float_Div\.qsys_edit\preferences.xml 195 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\sim\dspba_library.vhd 13298 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\sim\dspba_library_package.vhd 2713 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\sim\Float_Div_altera_fp_functions_171_45hiilq.vhd 441205 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\sim\Float_Div_altera_fp_functions_171_45hiilq_memoryC0_uid146_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\sim\Float_Div_altera_fp_functions_171_45hiilq_memoryC0_uid147_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\sim\Float_Div_altera_fp_functions_171_45hiilq_memoryC0_uid148_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\sim\Float_Div_altera_fp_functions_171_45hiilq_memoryC0_uid149_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\sim\Float_Div_altera_fp_functions_171_45hiilq_memoryC0_uid150_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\sim\Float_Div_altera_fp_functions_171_45hiilq_memoryC0_uid151_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\sim\Float_Div_altera_fp_functions_171_45hiilq_memoryC1_uid155_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\sim\Float_Div_altera_fp_functions_171_45hiilq_memoryC1_uid156_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\sim\Float_Div_altera_fp_functions_171_45hiilq_memoryC1_uid157_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\sim\Float_Div_altera_fp_functions_171_45hiilq_memoryC1_uid158_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\sim\Float_Div_altera_fp_functions_171_45hiilq_memoryC1_uid159_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\sim\Float_Div_altera_fp_functions_171_45hiilq_memoryC2_uid162_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\sim\Float_Div_altera_fp_functions_171_45hiilq_memoryC2_uid163_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\sim\Float_Div_altera_fp_functions_171_45hiilq_memoryC2_uid164_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\sim\Float_Div_altera_fp_functions_171_45hiilq_memoryC2_uid165_invTables_lutmem.hex 30750 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\sim\Float_Div_altera_fp_functions_171_45hiilq_memoryC3_uid168_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\sim\Float_Div_altera_fp_functions_171_45hiilq_memoryC3_uid169_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\sim\Float_Div_altera_fp_functions_171_45hiilq_memoryC3_uid170_invTables_lutmem.hex 30750 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\sim\Float_Div_altera_fp_functions_171_45hiilq_memoryC4_uid173_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\sim\Float_Div_altera_fp_functions_171_45hiilq_memoryC4_uid174_invTables_lutmem.hex 30750 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\synth\dspba_library.vhd 13298 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\synth\dspba_library_package.vhd 2713 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\synth\Float_Div_altera_fp_functions_171_45hiilq.vhd 441205 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\synth\Float_Div_altera_fp_functions_171_45hiilq_memoryC0_uid146_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\synth\Float_Div_altera_fp_functions_171_45hiilq_memoryC0_uid147_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\synth\Float_Div_altera_fp_functions_171_45hiilq_memoryC0_uid148_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\synth\Float_Div_altera_fp_functions_171_45hiilq_memoryC0_uid149_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\synth\Float_Div_altera_fp_functions_171_45hiilq_memoryC0_uid150_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\synth\Float_Div_altera_fp_functions_171_45hiilq_memoryC0_uid151_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\synth\Float_Div_altera_fp_functions_171_45hiilq_memoryC1_uid155_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\synth\Float_Div_altera_fp_functions_171_45hiilq_memoryC1_uid156_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\synth\Float_Div_altera_fp_functions_171_45hiilq_memoryC1_uid157_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\synth\Float_Div_altera_fp_functions_171_45hiilq_memoryC1_uid158_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\synth\Float_Div_altera_fp_functions_171_45hiilq_memoryC1_uid159_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\synth\Float_Div_altera_fp_functions_171_45hiilq_memoryC2_uid162_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\synth\Float_Div_altera_fp_functions_171_45hiilq_memoryC2_uid163_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\synth\Float_Div_altera_fp_functions_171_45hiilq_memoryC2_uid164_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\synth\Float_Div_altera_fp_functions_171_45hiilq_memoryC2_uid165_invTables_lutmem.hex 30750 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\synth\Float_Div_altera_fp_functions_171_45hiilq_memoryC3_uid168_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\synth\Float_Div_altera_fp_functions_171_45hiilq_memoryC3_uid169_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\synth\Float_Div_altera_fp_functions_171_45hiilq_memoryC3_uid170_invTables_lutmem.hex 30750 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\synth\Float_Div_altera_fp_functions_171_45hiilq_memoryC4_uid173_invTables_lutmem.hex 34846 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\altera_fp_functions_171\synth\Float_Div_altera_fp_functions_171_45hiilq_memoryC4_uid174_invTables_lutmem.hex 30750 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\Float_Div.bsf 3910 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\Float_Div.cmp 429 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\Float_Div.csv 3991 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\Float_Div.html 8097 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\Float_Div.ppf 507 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\Float_Div.qgsimc 7535 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\Float_Div.qgsynthc 7535 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\Float_Div.qip 20635 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\Float_Div.sopcinfo 23376 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\Float_Div.spd 4202 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\Float_Div.xml 17916 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\Float_Div_bb.v 248 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\Float_Div_generation.rpt 6450 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\Float_Div_inst.v 374 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\Float_Div_inst.vhd 712 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\sim\aldec\rivierapro_setup.tcl 20912 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\sim\Float_Div.v 677 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\sim\mentor\msim_setup.tcl 21589 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div\synth\Float_Div.v 677 2018-01-23
rtl\00_ip_core\Float_Div\Float_Div.ip 29874 2018-01-23
rtl\00_ip_core\Float_Multiply\.qsys_edit\filters.xml 66 2018-01-18
rtl\00_ip_core\Float_Multiply\.qsys_edit\Float_Multiply.xml 92709 2018-01-18

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