搜索资源列表
async_fifo.v
- the verilog model of async_fifo.
crc16_8bit.v
- 利用verilog硬件描述语言编写的8为并行输入的常crc校验模块。hdlc子模块
ANN_weight_connect.v
- 用VERILOG语言编写的神经元权值连接的源代码,供大家享用,但是注释很少.
verilog
- 一个桶形移位寄存器的.v文件，含testbench
MEDIAN.v
- fpga 的 median的verilog实现-median of verilog implementation
wm8731_zhengxianbo
- 讲诉了如何编写VERILOG程序通过DE2开发板的wm8731芯片产生正弦波-Talk about how to write VERILOG v. procedure DE2 development board wm8731 chip generated sine wave
Verilog-HDL-code
- verilog 经典例子的源码 非常适用于初学verilog的朋友们-classic example of verilog source code
verilog
- 里面有一百多个verilog实例 深入浅出的讲述了vrilog硬件描述语言的开发过程 成语代码以word 形式 -There are more than 100 verilog examples described in simple terms vrilog hardware descr iption language code of the development process in order to word the form of idioms
LatticeMico8_v3_0_Verilog
- The LatticeMico8™ is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice. Combining a full 18-bit wide instruction set with 16 or 32 General Purpose r
Xil3SD1800A_MIG_simplifiedUI_vlog_v92
- verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
clock
- verilog program for real time clock.. select the .v file to view the code.
cam_verilog.v.tar
- verilog source code for cam functionality
seqdetector1001.v.tar
- 1001 sequence detector in verilog code for mealy state machine
verilog
- 包含了许多verilog编程的实用例子，且有运行之后的V文件，很完整-verilog
LIP1733CORE_system_vbus_arbiter
- Verilog V Bus arbiter module
DAC-use-verilog
- 用verilog写的TLV5620芯片的DAC转换代码，核心文件dac.v，能进行实现，不仅仅是行为级描述-Written with verilog conversion code TLV5620 DAC chip, the core file dac.v, can be achieved, not just behavioral descr iption
apb.v
- AMBA总线apb总线的verilog代码以及相关的中断控制。(AMBA bus apb bus verilog code and associated interrupt control.)
verilog
- 8位计数器，可以实现计数器的相关功能，内涵verilog文件和testbench文件(8 bits counter,include v and testbech files ,has the ability of 8 bits counter)
v
- statistical signal processing,verilog
float_mult32x32.v
- verilog 语言写的FPGA内部实现硬件浮点乘法器的源码，两个时钟周期完成一次浮点乘法运算(The FPGA language written in Verilog implements the source of the hardware floating point multiplier, and completes the floating point multiplication operation in two clock cycles.)